Handle stack spills in ARM integrated assembler.

src/DartARM32/assembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe
 // Please update the (git) revision if we merge changes from Dart.
 // https://code.google.com/p/dart/wiki/GettingTheSource
 
 #include "vm/globals.h"  // NOLINT
 #if defined(TARGET_ARCH_ARM)
@@ skipping 54 matching lines @@
   }
 }
 
 
 void Assembler::Emit(int32_t value) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   buffer_.Emit<int32_t>(value);
 }
 
 #if 0
-// Moved to class AssemblerARM32.
+// Moved to ARM32::AssemblerARM32::emitType01()
 void Assembler::EmitType01(Condition cond,
                            int type,
                            Opcode opcode,
                            int set_cc,
                            Register rn,
                            Register rd,
                            Operand o) {
   ASSERT(rd != kNoRegister);
   ASSERT(cond != kNoCondition);
   int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
                      type << kTypeShift |
                      static_cast<int32_t>(opcode) << kOpcodeShift |
                      set_cc << kSShift |
                      static_cast<int32_t>(rn) << kRnShift |
                      static_cast<int32_t>(rd) << kRdShift |
                      o.encoding();
   Emit(encoding);
 }
 #endif
 
 void Assembler::EmitType5(Condition cond, int32_t offset, bool link) {
   ASSERT(cond != kNoCondition);
   int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
                      5 << kTypeShift |
                      (link ? 1 : 0) << kLinkShift;
   Emit(Assembler::EncodeBranchOffset(offset, encoding));
 }
 
 
+#if 0
+// Moved to ARM32::AssemblerARM32::emitMemOp()
 void Assembler::EmitMemOp(Condition cond,
                           bool load,
                           bool byte,
                           Register rd,
                           Address ad) {
   ASSERT(rd != kNoRegister);
   ASSERT(cond != kNoCondition);
   int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
                      B26 | (ad.kind() == Address::Immediate ? 0 : B25) |
                      (load ? L : 0) |
                      (byte ? B : 0) |
                      (static_cast<int32_t>(rd) << kRdShift) |
                      ad.encoding();
   Emit(encoding);
 }
-
+#endif
 
 void Assembler::EmitMemOpAddressMode3(Condition cond,
                                       int32_t mode,
                                       Register rd,
                                       Address ad) {
   ASSERT(rd != kNoRegister);
   ASSERT(cond != kNoCondition);
   int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
                      mode |
                      (static_cast<int32_t>(rd) << kRdShift) |
@@ skipping 56 matching lines @@
 
 void Assembler::and_(Register rd, Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), AND, 0, rn, rd, o);
 }
 
 
 void Assembler::eor(Register rd, Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), EOR, 0, rn, rd, o);
 }
 
-
+#if 0
+// Moved to ARM32::AssemberARM32::sub()
 void Assembler::sub(Register rd, Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), SUB, 0, rn, rd, o);
 }
+#endif
 
 void Assembler::rsb(Register rd, Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), RSB, 0, rn, rd, o);
 }
 
 void Assembler::rsbs(Register rd, Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), RSB, 1, rn, rd, o);
 }
 
 
 #if 0
-// Moved to IceAssemberARM32::add.
+// Moved to ARM32::AssemberARM32::add()
 void Assembler::add(Register rd, Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), ADD, 0, rn, rd, o);
 }
 
-
+// Moved to ARM32::AssemberARM32::add()
 void Assembler::adds(Register rd, Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), ADD, 1, rn, rd, o);
 }
-#endif
+#if 0

[Jim Stichnoth, 2015/10/15 20:41:29]

#endif ?

[Karl, 2015/10/15 22:03:33]

Done.

 
-
+#if 0
+// Moved to ARM32::AssemberARM32::sub()
 void Assembler::subs(Register rd, Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), SUB, 1, rn, rd, o);
 }
-
+#endif
 
 void Assembler::adc(Register rd, Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), ADC, 0, rn, rd, o);
 }
 
 
 void Assembler::adcs(Register rd, Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), ADC, 1, rn, rd, o);
 }
 
@@ skipping 219 matching lines @@
 void Assembler::sdiv(Register rd, Register rn, Register rm, Condition cond) {
   EmitDivOp(cond, 0, rd, rn, rm);
 }
 
 
 void Assembler::udiv(Register rd, Register rn, Register rm, Condition cond) {
   EmitDivOp(cond, B21 , rd, rn, rm);
 }
 
 
+#if 0
+// Moved to ARM32::AssemblerARM32::ldr()
 void Assembler::ldr(Register rd, Address ad, Condition cond) {
   EmitMemOp(cond, true, false, rd, ad);
 }
 
-
+// Moved to ARM32::AssemblerARM32::str()
 void Assembler::str(Register rd, Address ad, Condition cond) {
   EmitMemOp(cond, false, false, rd, ad);
 }
 
-
+// Moved to ARM32::AssemblerARM32::ldr()
 void Assembler::ldrb(Register rd, Address ad, Condition cond) {
   EmitMemOp(cond, true, true, rd, ad);
 }
 
-
+// Moved to ARM32::AssemblerARM32::str()
 void Assembler::strb(Register rd, Address ad, Condition cond) {
   EmitMemOp(cond, false, true, rd, ad);
 }
-
+#endif
 
 void Assembler::ldrh(Register rd, Address ad, Condition cond) {
   EmitMemOpAddressMode3(cond, L | B7 | H | B4, rd, ad);
 }
 
 
 void Assembler::strh(Register rd, Address ad, Condition cond) {
   EmitMemOpAddressMode3(cond, B7 | H | B4, rd, ad);
 }
 
@@ skipping 938 matching lines @@
   EmitSIMDqqq(B24 | B9 | B8, sz, qd, qn, qm);
 }
 
 
 void Assembler::vcgtqs(QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B24 | B21 | B11 | B10 | B9, kSWord, qd, qn, qm);
 }
 
 
 #if 0
-// Moved to: ARM32::AssemblerARM32.
+// Moved to: ARM32::AssemblerARM32::bkpt()
 void Assembler::bkpt(uint16_t imm16) {
   Emit(BkptEncoding(imm16));
 }
 #endif
 
 
 void Assembler::b(Label* label, Condition cond) {
   EmitBranch(cond, label, false);
 }
 
 
 void Assembler::bl(Label* label, Condition cond) {
   EmitBranch(cond, label, true);
 }
 
 #if 0
-// Moved to: ARM32::AssemblerARM32.
+// Moved to: ARM32::AssemblerARM32::bx()
 void Assembler::bx(Register rm, Condition cond) {
   ASSERT(rm != kNoRegister);
   ASSERT(cond != kNoCondition);
   int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
                      B24 | B21 | (0xfff << 8) | B4 |
                      (static_cast<int32_t>(rm) << kRmShift);
   Emit(encoding);
 }
 #endif
 
@@ skipping 848 matching lines @@
       int32_t next = buffer_.Load<int32_t>(position);
       int32_t encoded = Assembler::EncodeBranchOffset(dest, next);
       buffer_.Store<int32_t>(position, encoded);
       label->position_ = Assembler::DecodeBranchOffset(next);
     }
   }
   label->BindTo(bound_pc);
 }
 
 #if 0
-// Moved to: ARM32::AssemblerARM32 as method bind(Label* Label)
+// Moved to: ARM32::AssemblerARM32::bind(Label* Label)
 // Note: Most of this code isn't needed because instruction selection has
 // already been handler
 void Assembler::BindARMv7(Label* label) {
   ASSERT(!label->IsBound());
   intptr_t bound_pc = buffer_.Size();
   while (label->IsLinked()) {
     const int32_t position = label->Position();
     int32_t dest = bound_pc - position;
     if (use_far_branches() && !CanEncodeBranchOffset(dest)) {
       // Far branches are enabled and we can't encode the branch offset.
@@ skipping 1319 matching lines @@
 
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
   return fpu_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM