Fix emission of move immediate for ARM integrated assembler.

src/IceAssemblerARM32.h

 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// This file implements the Assembler class for ARM32.
 ///
+/// Note: All references to ARM "section" documentation refers to the "ARM
+/// Architecture Reference Manual, ARMv7-A and ARMv7-R edition". See:
+/// http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0406c
+///
 //===----------------------------------------------------------------------===//
 
 #ifndef SUBZERO_SRC_ICEASSEMBLERARM32_H
 #define SUBZERO_SRC_ICEASSEMBLERARM32_H
 
 #include "IceAssembler.h"
 #include "IceConditionCodesARM32.h"
 #include "IceDefs.h"
 #include "IceFixups.h"
+#include "IceInstARM32.h"
 #include "IceRegistersARM32.h"
 #include "IceTargetLowering.h"
 
 namespace Ice {
 namespace ARM32 {
 
 class AssemblerARM32 : public Assembler {
   AssemblerARM32(const AssemblerARM32 &) = delete;
   AssemblerARM32 &operator=(const AssemblerARM32 &) = delete;
 
@@ skipping 27 matching lines @@
     static const uint8_t Padding[] = {0xE7, 0xFE, 0xDE, 0xF0};
     return llvm::ArrayRef<uint8_t>(Padding, 4);
   }
 
   void padWithNop(intptr_t Padding) override {
     (void)Padding;
     llvm_unreachable("Not yet implemented.");
   }
 
   Ice::Label *getCfgNodeLabel(SizeT NodeNumber) override {
-    (void)NodeNumber;
-    llvm_unreachable("Not yet implemented.");
+    assert(NodeNumber < CfgNodeLabels.size());
+    return CfgNodeLabels[NodeNumber];
   }
 
   void bindCfgNodeLabel(SizeT NodeNumber) override {
     assert(!getPreliminary());
     Label *L = getOrCreateCfgNodeLabel(NodeNumber);
     this->bind(L);
   }
 
   bool fixupIsPCRel(FixupKind Kind) const override {
     (void)Kind;
     llvm_unreachable("Not yet implemented.");
   }
   void bind(Label *label);
 
-  void bkpt(uint16_t imm16);
+  void bkpt(uint16_t Imm16);
 
-  void bx(RegARM32::GPRRegister rm, CondARM32::Cond cond = CondARM32::AL);
+  void mov(RegARM32::GPRRegister Rd, const OperandARM32FlexImm &FlexImm,
+           CondARM32::Cond Cond);
+
+  void bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond = CondARM32::AL);
 
   static bool classof(const Assembler *Asm) {
     return Asm->getKind() == Asm_ARM32;
   }
 
 private:
   // Instruction encoding bits.
 
   // halfword (or byte)
   static constexpr uint32_t H = 1 << 5;
@@ skipping 39 matching lines @@
   static constexpr uint32_t B20 = 1 << 20;
   static constexpr uint32_t B21 = 1 << 21;
   static constexpr uint32_t B22 = 1 << 22;
   static constexpr uint32_t B23 = 1 << 23;
   static constexpr uint32_t B24 = 1 << 24;
   static constexpr uint32_t B25 = 1 << 25;
   static constexpr uint32_t B26 = 1 << 26;
   static constexpr uint32_t B27 = 1 << 27;
 
   // Constants used for the decoding or encoding of the individual fields of
-  // instructions. Based on section A5.1 from the "ARM Architecture Reference
-  // Manual, ARMv7-A and ARMv7-R edition". See:
-  // http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0406c
+  // instructions. Based on ARM section A5.1.
   static constexpr uint32_t kConditionShift = 28;
   static constexpr uint32_t kConditionBits = 4;
   static constexpr uint32_t kTypeShift = 25;
   static constexpr uint32_t kTypeBits = 3;
   static constexpr uint32_t kLinkShift = 24;
   static constexpr uint32_t kLinkBits = 1;
   static constexpr uint32_t kUShift = 23;
   static constexpr uint32_t kUBits = 1;
   static constexpr uint32_t kOpcodeShift = 21;
   static constexpr uint32_t kOpcodeBits = 4;
@@ skipping 52 matching lines @@
   static constexpr uint32_t kCRmBits = 4;
   static constexpr uint32_t kOpc2Shift = 5;
   static constexpr uint32_t kOpc2Bits = 3;
   static constexpr uint32_t kCoprocShift = 8;
   static constexpr uint32_t kCoprocBits = 4;
   static constexpr uint32_t kCRnShift = 16;
   static constexpr uint32_t kCRnBits = 4;
   static constexpr uint32_t kOpc1Shift = 21;
   static constexpr uint32_t kOpc1Bits = 3;
 
+  // Types of instructions.
+  static constexpr uint32_t kInstTypeReg = 0;
+  static constexpr uint32_t kInstTypeImmediate = 1;
+
   static constexpr uint32_t kBranchOffsetMask = 0x00ffffff;
 
+  // Converts from bool to bit.

[John, 2015/10/12 20:45:27]

optional: All of these helpers are part of the assembler's implementation. given
that they are static methods, I would just define them as free functions in
unnamed namespaces in the .cpp file. (same for the constexprs above.)

[Karl, 2015/10/12 21:24:56]

Done.

+  static uint32_t encodeBool(bool b) { return b ? 1 : 0; }
+
+  // Converts rotated immediate into imm12.
+  static uint32_t encodeImm12FromFlexImm(const OperandARM32FlexImm &FlexImm) {
+    uint32_t Immed8 = FlexImm.getImm();
+    uint32_t Rotate = FlexImm.getRotateAmt();
+    assert((Rotate < (1 << kRotateBits)) && (Immed8 < (1 << kImmed8Bits)));
+    return (Rotate << kRotateShift) | (Immed8 << kImmed8Shift);
+  }
+
+  static bool isGPRRegisterDefined(uint32_t R) {
+    return R != encodeGPRRegister(RegARM32::Encoded_Not_GPR);
+  }
+
+  static uint32_t encodeGPRRegister(RegARM32::GPRRegister Rn) {
+    return static_cast<uint32_t>(Rn);
+  }
+
+  static bool isConditionDefined(CondARM32::Cond Cond) {
+    return Cond != CondARM32::kNone;
+  }
+
+  static uint32_t encodeCondition(CondARM32::Cond Cond) {
+    return static_cast<uint32_t>(Cond);
+  }
+
   // A vector of pool-allocated x86 labels for CFG nodes.
   using LabelVector = std::vector<Label *>;
   LabelVector CfgNodeLabels;
 
   Label *getOrCreateLabel(SizeT Number, LabelVector &Labels);
   Label *getOrCreateCfgNodeLabel(SizeT NodeNumber) {
     return getOrCreateLabel(NodeNumber, CfgNodeLabels);
   }
 
-  void emitInt32(int32_t Value) { Buffer.emit<int32_t>(Value); }
+  void emitInt32(uint32_t Value) { Buffer.emit<uint32_t>(Value); }
+
+  // Pattern cccctttoooosnnnnddddiiiiiiiiiiii where cccc=Cond, ttt=Type,
+  // oooo=Opcode, nnnn=Rn, dddd=Rd, iiiiiiiiiiii=imm12 (See ARM section A5.2.3).
+  void emitType01(CondARM32::Cond Cond, uint32_t Type, uint32_t Opcode,
+                  bool SetCc, uint32_t Rn, uint32_t Rd, uint32_t imm12);
 
   static int32_t BkptEncoding(uint16_t imm16) {
     // bkpt requires that the cond field is AL.
     // cccc00010010iiiiiiiiiiii0111iiii where cccc=AL and i in imm16
     return (CondARM32::AL << kConditionShift) | B24 | B21 |
            ((imm16 >> 4) << 8) | B6 | B5 | B4 | (imm16 & 0xf);
   }
 };
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H