tests_lit/llvm2ice_tests/64bit.pnacl.ll - Issue 1392383003: Subzero: Consider all instruction variables for register preference.

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Unified Diff: tests_lit/llvm2ice_tests/64bit.pnacl.ll

Issue 1392383003: Subzero: Consider all instruction variables for register preference. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master

Patch Set: Created 5 years, 2 months ago

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Index: tests_lit/llvm2ice_tests/64bit.pnacl.ll

diff --git a/tests_lit/llvm2ice_tests/64bit.pnacl.ll b/tests_lit/llvm2ice_tests/64bit.pnacl.ll

index 19d6e70a25d5e912445f210483f98d5bebf14707..0666e66966276683593843f85e7abf01c3a683a9 100644

--- a/tests_lit/llvm2ice_tests/64bit.pnacl.ll

+++ b/tests_lit/llvm2ice_tests/64bit.pnacl.ll

@@ -514,10 +514,10 @@ entry:

; ARM32-LABEL: shr64BitSigned

; ARM32: lsr [[T0:r[0-9]+]], r0, r2

; ARM32: rsb [[T1:r[0-9]+]], r2, #32

-; ARM32: orr r0, [[T0]], r1, lsl [[T1]]

+; ARM32: orr [[T3:r[0-9]+]], [[T0]], r1, lsl [[T1]]

John 2015/10/12 15:35:17 why/how did this change?

Jim Stichnoth 2015/10/12 17:27:31 Turns out it shouldn't have changed, and the "brea

; ARM32: sub [[T2:r[0-9]+]], r2, #32

; ARM32: cmp [[T2]], #0

-; ARM32: asrge r0, r1, [[T2]]

+; ARM32: asrge [[T3]], r1, [[T2]]

; ARM32: asr r{{[0-9]+}}, r1, r2

define internal i32 @shr64BitSignedTrunc(i64 %a, i64 %b) {

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