Subzero: Consider all instruction variables for register preference.

src/IceInstARM32.h

 //===- subzero/src/IceInstARM32.h - ARM32 machine instructions --*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 1134 matching lines @@
 public:
   static InstARM32Mov *create(Cfg *Func, Variable *Dest, Operand *Src,
                               CondARM32::Cond Predicate) {
     return new (Func->allocate<InstARM32Mov>())
         InstARM32Mov(Func, Dest, Src, Predicate);
   }
   bool isRedundantAssign() const override {
     return !isMultiDest() && !isMultiSource() &&
            checkForRedundantAssign(getDest(), getSrc(0));
   }
-  bool isSimpleAssign() const override { return true; }
+  bool isVarAssign() const override { return llvm::isa<Variable>(getSrc(0)); }
   void emit(const Cfg *Func) const override;
   void emitIAS(const Cfg *Func) const override;
   void dump(const Cfg *Func) const override;
   static bool classof(const Inst *Inst) { return isClassof(Inst, Mov); }
 
   bool isMultiDest() const { return DestHi != nullptr; }
 
   bool isMultiSource() const {
     assert(getSrcSize() == 1 || getSrcSize() == 2);
     return getSrcSize() == 2;
@@ skipping 95 matching lines @@
 // default implementations. Without this, there is the possibility of ODR
 // violations and link errors.
 
 template <> void InstARM32Ldr::emit(const Cfg *Func) const;
 template <> void InstARM32Movw::emit(const Cfg *Func) const;
 template <> void InstARM32Movt::emit(const Cfg *Func) const;
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEINSTARM32_H