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Unified Diff: tests_lit/reader_tests/nacl-atomic-intrinsics.ll

Issue 1387963002: Make sure that all globals are internal, except for "start" functions. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fix nit. Created 5 years, 2 months ago
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Index: tests_lit/reader_tests/nacl-atomic-intrinsics.ll
diff --git a/tests_lit/reader_tests/nacl-atomic-intrinsics.ll b/tests_lit/reader_tests/nacl-atomic-intrinsics.ll
index b59b380e7fc5b9956e5b460e8fe4f021e68534fe..d12c723891b0193a4e782a0c0a6218ad41bfb933 100644
--- a/tests_lit/reader_tests/nacl-atomic-intrinsics.ll
+++ b/tests_lit/reader_tests/nacl-atomic-intrinsics.ll
@@ -28,7 +28,7 @@ declare i1 @llvm.nacl.atomic.is.lock.free(i32, i8*)
;;; Load
-define i32 @test_atomic_load_8(i32 %iptr) {
+define internal i32 @test_atomic_load_8(i32 %iptr) {
entry:
%ptr = inttoptr i32 %iptr to i8*
; parameter value "6" is for the sequential consistency memory order.
@@ -37,14 +37,14 @@ entry:
ret i32 %r
}
-; CHECK: define i32 @test_atomic_load_8(i32 %iptr) {
+; CHECK: define internal i32 @test_atomic_load_8(i32 %iptr) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %i = call i8 @llvm.nacl.atomic.load.i8(i32 %iptr, i32 6)
; CHECK-NEXT: %r = zext i8 %i to i32
; CHECK-NEXT: ret i32 %r
; CHECK-NEXT: }
-define i32 @test_atomic_load_16(i32 %iptr) {
+define internal i32 @test_atomic_load_16(i32 %iptr) {
entry:
%ptr = inttoptr i32 %iptr to i16*
%i = call i16 @llvm.nacl.atomic.load.i16(i16* %ptr, i32 6)
@@ -52,34 +52,34 @@ entry:
ret i32 %r
}
-; CHECK-NEXT: define i32 @test_atomic_load_16(i32 %iptr) {
+; CHECK-NEXT: define internal i32 @test_atomic_load_16(i32 %iptr) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %i = call i16 @llvm.nacl.atomic.load.i16(i32 %iptr, i32 6)
; CHECK-NEXT: %r = zext i16 %i to i32
; CHECK-NEXT: ret i32 %r
; CHECK-NEXT: }
-define i32 @test_atomic_load_32(i32 %iptr) {
+define internal i32 @test_atomic_load_32(i32 %iptr) {
entry:
%ptr = inttoptr i32 %iptr to i32*
%r = call i32 @llvm.nacl.atomic.load.i32(i32* %ptr, i32 6)
ret i32 %r
}
-; CHECK-NEXT: define i32 @test_atomic_load_32(i32 %iptr) {
+; CHECK-NEXT: define internal i32 @test_atomic_load_32(i32 %iptr) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %r = call i32 @llvm.nacl.atomic.load.i32(i32 %iptr, i32 6)
; CHECK-NEXT: ret i32 %r
; CHECK-NEXT: }
-define i64 @test_atomic_load_64(i32 %iptr) {
+define internal i64 @test_atomic_load_64(i32 %iptr) {
entry:
%ptr = inttoptr i32 %iptr to i64*
%r = call i64 @llvm.nacl.atomic.load.i64(i64* %ptr, i32 6)
ret i64 %r
}
-; CHECK-NEXT: define i64 @test_atomic_load_64(i32 %iptr) {
+; CHECK-NEXT: define internal i64 @test_atomic_load_64(i32 %iptr) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %r = call i64 @llvm.nacl.atomic.load.i64(i32 %iptr, i32 6)
; CHECK-NEXT: ret i64 %r
@@ -87,7 +87,7 @@ entry:
;;; Store
-define void @test_atomic_store_8(i32 %iptr, i32 %v) {
+define internal void @test_atomic_store_8(i32 %iptr, i32 %v) {
entry:
%truncv = trunc i32 %v to i8
%ptr = inttoptr i32 %iptr to i8*
@@ -95,14 +95,14 @@ entry:
ret void
}
-; CHECK-NEXT: define void @test_atomic_store_8(i32 %iptr, i32 %v) {
+; CHECK-NEXT: define internal void @test_atomic_store_8(i32 %iptr, i32 %v) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %truncv = trunc i32 %v to i8
; CHECK-NEXT: call void @llvm.nacl.atomic.store.i8(i8 %truncv, i32 %iptr, i32 6)
; CHECK-NEXT: ret void
; CHECK-NEXT: }
-define void @test_atomic_store_16(i32 %iptr, i32 %v) {
+define internal void @test_atomic_store_16(i32 %iptr, i32 %v) {
entry:
%truncv = trunc i32 %v to i16
%ptr = inttoptr i32 %iptr to i16*
@@ -110,47 +110,47 @@ entry:
ret void
}
-; CHECK-NEXT: define void @test_atomic_store_16(i32 %iptr, i32 %v) {
+; CHECK-NEXT: define internal void @test_atomic_store_16(i32 %iptr, i32 %v) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %truncv = trunc i32 %v to i16
; CHECK-NEXT: call void @llvm.nacl.atomic.store.i16(i16 %truncv, i32 %iptr, i32 6)
; CHECK-NEXT: ret void
; CHECK-NEXT: }
-define void @test_atomic_store_32(i32 %iptr, i32 %v) {
+define internal void @test_atomic_store_32(i32 %iptr, i32 %v) {
entry:
%ptr = inttoptr i32 %iptr to i32*
call void @llvm.nacl.atomic.store.i32(i32 %v, i32* %ptr, i32 6)
ret void
}
-; CHECK-NEXT: define void @test_atomic_store_32(i32 %iptr, i32 %v) {
+; CHECK-NEXT: define internal void @test_atomic_store_32(i32 %iptr, i32 %v) {
; CHECK-NEXT: entry:
; CHECK-NEXT: call void @llvm.nacl.atomic.store.i32(i32 %v, i32 %iptr, i32 6)
; CHECK-NEXT: ret void
; CHECK-NEXT: }
-define void @test_atomic_store_64(i32 %iptr, i64 %v) {
+define internal void @test_atomic_store_64(i32 %iptr, i64 %v) {
entry:
%ptr = inttoptr i32 %iptr to i64*
call void @llvm.nacl.atomic.store.i64(i64 %v, i64* %ptr, i32 6)
ret void
}
-; CHECK-NEXT: define void @test_atomic_store_64(i32 %iptr, i64 %v) {
+; CHECK-NEXT: define internal void @test_atomic_store_64(i32 %iptr, i64 %v) {
; CHECK-NEXT: entry:
; CHECK-NEXT: call void @llvm.nacl.atomic.store.i64(i64 %v, i32 %iptr, i32 6)
; CHECK-NEXT: ret void
; CHECK-NEXT: }
-define void @test_atomic_store_64_const(i32 %iptr) {
+define internal void @test_atomic_store_64_const(i32 %iptr) {
entry:
%ptr = inttoptr i32 %iptr to i64*
call void @llvm.nacl.atomic.store.i64(i64 12345678901234, i64* %ptr, i32 6)
ret void
}
-; CHECK-NEXT: define void @test_atomic_store_64_const(i32 %iptr) {
+; CHECK-NEXT: define internal void @test_atomic_store_64_const(i32 %iptr) {
; CHECK-NEXT: entry:
; CHECK-NEXT: call void @llvm.nacl.atomic.store.i64(i64 12345678901234, i32 %iptr, i32 6)
; CHECK-NEXT: ret void
@@ -160,7 +160,7 @@ entry:
;; add
-define i32 @test_atomic_rmw_add_8(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_add_8(i32 %iptr, i32 %v) {
entry:
%trunc = trunc i32 %v to i8
%ptr = inttoptr i32 %iptr to i8*
@@ -170,7 +170,7 @@ entry:
ret i32 %a_ext
}
-; CHECK-NEXT: define i32 @test_atomic_rmw_add_8(i32 %iptr, i32 %v) {
+; CHECK-NEXT: define internal i32 @test_atomic_rmw_add_8(i32 %iptr, i32 %v) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %trunc = trunc i32 %v to i8
; CHECK-NEXT: %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 1, i32 %iptr, i8 %trunc, i32 6)
@@ -178,7 +178,7 @@ entry:
; CHECK-NEXT: ret i32 %a_ext
; CHECK-NEXT: }
-define i32 @test_atomic_rmw_add_16(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_add_16(i32 %iptr, i32 %v) {
entry:
%trunc = trunc i32 %v to i16
%ptr = inttoptr i32 %iptr to i16*
@@ -187,7 +187,7 @@ entry:
ret i32 %a_ext
}
-; CHECK-NEXT: define i32 @test_atomic_rmw_add_16(i32 %iptr, i32 %v) {
+; CHECK-NEXT: define internal i32 @test_atomic_rmw_add_16(i32 %iptr, i32 %v) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %trunc = trunc i32 %v to i16
; CHECK-NEXT: %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 1, i32 %iptr, i16 %trunc, i32 6)
@@ -195,27 +195,27 @@ entry:
; CHECK-NEXT: ret i32 %a_ext
; CHECK-NEXT: }
-define i32 @test_atomic_rmw_add_32(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_add_32(i32 %iptr, i32 %v) {
entry:
%ptr = inttoptr i32 %iptr to i32*
%a = call i32 @llvm.nacl.atomic.rmw.i32(i32 1, i32* %ptr, i32 %v, i32 6)
ret i32 %a
}
-; CHECK-NEXT: define i32 @test_atomic_rmw_add_32(i32 %iptr, i32 %v) {
+; CHECK-NEXT: define internal i32 @test_atomic_rmw_add_32(i32 %iptr, i32 %v) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 1, i32 %iptr, i32 %v, i32 6)
; CHECK-NEXT: ret i32 %a
; CHECK-NEXT: }
-define i64 @test_atomic_rmw_add_64(i32 %iptr, i64 %v) {
+define internal i64 @test_atomic_rmw_add_64(i32 %iptr, i64 %v) {
entry:
%ptr = inttoptr i32 %iptr to i64*
%a = call i64 @llvm.nacl.atomic.rmw.i64(i32 1, i64* %ptr, i64 %v, i32 6)
ret i64 %a
}
-; CHECK-NEXT: define i64 @test_atomic_rmw_add_64(i32 %iptr, i64 %v) {
+; CHECK-NEXT: define internal i64 @test_atomic_rmw_add_64(i32 %iptr, i64 %v) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 1, i32 %iptr, i64 %v, i32 6)
; CHECK-NEXT: ret i64 %a
@@ -223,7 +223,7 @@ entry:
;; sub
-define i32 @test_atomic_rmw_sub_8(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_sub_8(i32 %iptr, i32 %v) {
entry:
%trunc = trunc i32 %v to i8
%ptr = inttoptr i32 %iptr to i8*
@@ -232,7 +232,7 @@ entry:
ret i32 %a_ext
}
-; CHECK-NEXT: define i32 @test_atomic_rmw_sub_8(i32 %iptr, i32 %v) {
+; CHECK-NEXT: define internal i32 @test_atomic_rmw_sub_8(i32 %iptr, i32 %v) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %trunc = trunc i32 %v to i8
; CHECK-NEXT: %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 2, i32 %iptr, i8 %trunc, i32 6)
@@ -240,7 +240,7 @@ entry:
; CHECK-NEXT: ret i32 %a_ext
; CHECK-NEXT: }
-define i32 @test_atomic_rmw_sub_16(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_sub_16(i32 %iptr, i32 %v) {
entry:
%trunc = trunc i32 %v to i16
%ptr = inttoptr i32 %iptr to i16*
@@ -249,7 +249,7 @@ entry:
ret i32 %a_ext
}
-; CHECK-NEXT: define i32 @test_atomic_rmw_sub_16(i32 %iptr, i32 %v) {
+; CHECK-NEXT: define internal i32 @test_atomic_rmw_sub_16(i32 %iptr, i32 %v) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %trunc = trunc i32 %v to i16
; CHECK-NEXT: %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 2, i32 %iptr, i16 %trunc, i32 6)
@@ -257,27 +257,27 @@ entry:
; CHECK-NEXT: ret i32 %a_ext
; CHECK-NEXT: }
-define i32 @test_atomic_rmw_sub_32(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_sub_32(i32 %iptr, i32 %v) {
entry:
%ptr = inttoptr i32 %iptr to i32*
%a = call i32 @llvm.nacl.atomic.rmw.i32(i32 2, i32* %ptr, i32 %v, i32 6)
ret i32 %a
}
-; CHECK-NEXT: define i32 @test_atomic_rmw_sub_32(i32 %iptr, i32 %v) {
+; CHECK-NEXT: define internal i32 @test_atomic_rmw_sub_32(i32 %iptr, i32 %v) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 2, i32 %iptr, i32 %v, i32 6)
; CHECK-NEXT: ret i32 %a
; CHECK-NEXT: }
-define i64 @test_atomic_rmw_sub_64(i32 %iptr, i64 %v) {
+define internal i64 @test_atomic_rmw_sub_64(i32 %iptr, i64 %v) {
entry:
%ptr = inttoptr i32 %iptr to i64*
%a = call i64 @llvm.nacl.atomic.rmw.i64(i32 2, i64* %ptr, i64 %v, i32 6)
ret i64 %a
}
-; CHECK-NEXT: define i64 @test_atomic_rmw_sub_64(i32 %iptr, i64 %v) {
+; CHECK-NEXT: define internal i64 @test_atomic_rmw_sub_64(i32 %iptr, i64 %v) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 2, i32 %iptr, i64 %v, i32 6)
; CHECK-NEXT: ret i64 %a
@@ -285,7 +285,7 @@ entry:
;; or
-define i32 @test_atomic_rmw_or_8(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_or_8(i32 %iptr, i32 %v) {
entry:
%trunc = trunc i32 %v to i8
%ptr = inttoptr i32 %iptr to i8*
@@ -294,7 +294,7 @@ entry:
ret i32 %a_ext
}
-; CHECK-NEXT: define i32 @test_atomic_rmw_or_8(i32 %iptr, i32 %v) {
+; CHECK-NEXT: define internal i32 @test_atomic_rmw_or_8(i32 %iptr, i32 %v) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %trunc = trunc i32 %v to i8
; CHECK-NEXT: %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 3, i32 %iptr, i8 %trunc, i32 6)
@@ -302,7 +302,7 @@ entry:
; CHECK-NEXT: ret i32 %a_ext
; CHECK-NEXT: }
-define i32 @test_atomic_rmw_or_16(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_or_16(i32 %iptr, i32 %v) {
entry:
%trunc = trunc i32 %v to i16
%ptr = inttoptr i32 %iptr to i16*
@@ -311,7 +311,7 @@ entry:
ret i32 %a_ext
}
-; CHECK-NEXT: define i32 @test_atomic_rmw_or_16(i32 %iptr, i32 %v) {
+; CHECK-NEXT: define internal i32 @test_atomic_rmw_or_16(i32 %iptr, i32 %v) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %trunc = trunc i32 %v to i16
; CHECK-NEXT: %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 3, i32 %iptr, i16 %trunc, i32 6)
@@ -319,27 +319,27 @@ entry:
; CHECK-NEXT: ret i32 %a_ext
; CHECK-NEXT: }
-define i32 @test_atomic_rmw_or_32(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_or_32(i32 %iptr, i32 %v) {
entry:
%ptr = inttoptr i32 %iptr to i32*
%a = call i32 @llvm.nacl.atomic.rmw.i32(i32 3, i32* %ptr, i32 %v, i32 6)
ret i32 %a
}
-; CHECK-NEXT: define i32 @test_atomic_rmw_or_32(i32 %iptr, i32 %v) {
+; CHECK-NEXT: define internal i32 @test_atomic_rmw_or_32(i32 %iptr, i32 %v) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 3, i32 %iptr, i32 %v, i32 6)
; CHECK-NEXT: ret i32 %a
; CHECK-NEXT: }
-define i64 @test_atomic_rmw_or_64(i32 %iptr, i64 %v) {
+define internal i64 @test_atomic_rmw_or_64(i32 %iptr, i64 %v) {
entry:
%ptr = inttoptr i32 %iptr to i64*
%a = call i64 @llvm.nacl.atomic.rmw.i64(i32 3, i64* %ptr, i64 %v, i32 6)
ret i64 %a
}
-; CHECK-NEXT: define i64 @test_atomic_rmw_or_64(i32 %iptr, i64 %v) {
+; CHECK-NEXT: define internal i64 @test_atomic_rmw_or_64(i32 %iptr, i64 %v) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 3, i32 %iptr, i64 %v, i32 6)
; CHECK-NEXT: ret i64 %a
@@ -347,7 +347,7 @@ entry:
;; and
-define i32 @test_atomic_rmw_and_8(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_and_8(i32 %iptr, i32 %v) {
entry:
%trunc = trunc i32 %v to i8
%ptr = inttoptr i32 %iptr to i8*
@@ -356,7 +356,7 @@ entry:
ret i32 %a_ext
}
-; CHECK-NEXT: define i32 @test_atomic_rmw_and_8(i32 %iptr, i32 %v) {
+; CHECK-NEXT: define internal i32 @test_atomic_rmw_and_8(i32 %iptr, i32 %v) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %trunc = trunc i32 %v to i8
; CHECK-NEXT: %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 4, i32 %iptr, i8 %trunc, i32 6)
@@ -364,7 +364,7 @@ entry:
; CHECK-NEXT: ret i32 %a_ext
; CHECK-NEXT: }
-define i32 @test_atomic_rmw_and_16(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_and_16(i32 %iptr, i32 %v) {
entry:
%trunc = trunc i32 %v to i16
%ptr = inttoptr i32 %iptr to i16*
@@ -373,7 +373,7 @@ entry:
ret i32 %a_ext
}
-; CHECK-NEXT: define i32 @test_atomic_rmw_and_16(i32 %iptr, i32 %v) {
+; CHECK-NEXT: define internal i32 @test_atomic_rmw_and_16(i32 %iptr, i32 %v) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %trunc = trunc i32 %v to i16
; CHECK-NEXT: %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 4, i32 %iptr, i16 %trunc, i32 6)
@@ -381,27 +381,27 @@ entry:
; CHECK-NEXT: ret i32 %a_ext
; CHECK-NEXT: }
-define i32 @test_atomic_rmw_and_32(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_and_32(i32 %iptr, i32 %v) {
entry:
%ptr = inttoptr i32 %iptr to i32*
%a = call i32 @llvm.nacl.atomic.rmw.i32(i32 4, i32* %ptr, i32 %v, i32 6)
ret i32 %a
}
-; CHECK-NEXT: define i32 @test_atomic_rmw_and_32(i32 %iptr, i32 %v) {
+; CHECK-NEXT: define internal i32 @test_atomic_rmw_and_32(i32 %iptr, i32 %v) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 4, i32 %iptr, i32 %v, i32 6)
; CHECK-NEXT: ret i32 %a
; CHECK-NEXT: }
-define i64 @test_atomic_rmw_and_64(i32 %iptr, i64 %v) {
+define internal i64 @test_atomic_rmw_and_64(i32 %iptr, i64 %v) {
entry:
%ptr = inttoptr i32 %iptr to i64*
%a = call i64 @llvm.nacl.atomic.rmw.i64(i32 4, i64* %ptr, i64 %v, i32 6)
ret i64 %a
}
-; CHECK-NEXT: define i64 @test_atomic_rmw_and_64(i32 %iptr, i64 %v) {
+; CHECK-NEXT: define internal i64 @test_atomic_rmw_and_64(i32 %iptr, i64 %v) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 4, i32 %iptr, i64 %v, i32 6)
; CHECK-NEXT: ret i64 %a
@@ -409,7 +409,7 @@ entry:
;; xor
-define i32 @test_atomic_rmw_xor_8(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_xor_8(i32 %iptr, i32 %v) {
entry:
%trunc = trunc i32 %v to i8
%ptr = inttoptr i32 %iptr to i8*
@@ -418,7 +418,7 @@ entry:
ret i32 %a_ext
}
-; CHECK-NEXT: define i32 @test_atomic_rmw_xor_8(i32 %iptr, i32 %v) {
+; CHECK-NEXT: define internal i32 @test_atomic_rmw_xor_8(i32 %iptr, i32 %v) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %trunc = trunc i32 %v to i8
; CHECK-NEXT: %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 5, i32 %iptr, i8 %trunc, i32 6)
@@ -426,7 +426,7 @@ entry:
; CHECK-NEXT: ret i32 %a_ext
; CHECK-NEXT: }
-define i32 @test_atomic_rmw_xor_16(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_xor_16(i32 %iptr, i32 %v) {
entry:
%trunc = trunc i32 %v to i16
%ptr = inttoptr i32 %iptr to i16*
@@ -435,7 +435,7 @@ entry:
ret i32 %a_ext
}
-; CHECK-NEXT: define i32 @test_atomic_rmw_xor_16(i32 %iptr, i32 %v) {
+; CHECK-NEXT: define internal i32 @test_atomic_rmw_xor_16(i32 %iptr, i32 %v) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %trunc = trunc i32 %v to i16
; CHECK-NEXT: %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 5, i32 %iptr, i16 %trunc, i32 6)
@@ -443,27 +443,27 @@ entry:
; CHECK-NEXT: ret i32 %a_ext
; CHECK-NEXT: }
-define i32 @test_atomic_rmw_xor_32(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_xor_32(i32 %iptr, i32 %v) {
entry:
%ptr = inttoptr i32 %iptr to i32*
%a = call i32 @llvm.nacl.atomic.rmw.i32(i32 5, i32* %ptr, i32 %v, i32 6)
ret i32 %a
}
-; CHECK-NEXT: define i32 @test_atomic_rmw_xor_32(i32 %iptr, i32 %v) {
+; CHECK-NEXT: define internal i32 @test_atomic_rmw_xor_32(i32 %iptr, i32 %v) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 5, i32 %iptr, i32 %v, i32 6)
; CHECK-NEXT: ret i32 %a
; CHECK-NEXT: }
-define i64 @test_atomic_rmw_xor_64(i32 %iptr, i64 %v) {
+define internal i64 @test_atomic_rmw_xor_64(i32 %iptr, i64 %v) {
entry:
%ptr = inttoptr i32 %iptr to i64*
%a = call i64 @llvm.nacl.atomic.rmw.i64(i32 5, i64* %ptr, i64 %v, i32 6)
ret i64 %a
}
-; CHECK-NEXT: define i64 @test_atomic_rmw_xor_64(i32 %iptr, i64 %v) {
+; CHECK-NEXT: define internal i64 @test_atomic_rmw_xor_64(i32 %iptr, i64 %v) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 5, i32 %iptr, i64 %v, i32 6)
; CHECK-NEXT: ret i64 %a
@@ -471,7 +471,7 @@ entry:
;; exchange
-define i32 @test_atomic_rmw_xchg_8(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_xchg_8(i32 %iptr, i32 %v) {
entry:
%trunc = trunc i32 %v to i8
%ptr = inttoptr i32 %iptr to i8*
@@ -480,7 +480,7 @@ entry:
ret i32 %a_ext
}
-; CHECK-NEXT: define i32 @test_atomic_rmw_xchg_8(i32 %iptr, i32 %v) {
+; CHECK-NEXT: define internal i32 @test_atomic_rmw_xchg_8(i32 %iptr, i32 %v) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %trunc = trunc i32 %v to i8
; CHECK-NEXT: %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 6, i32 %iptr, i8 %trunc, i32 6)
@@ -488,7 +488,7 @@ entry:
; CHECK-NEXT: ret i32 %a_ext
; CHECK-NEXT: }
-define i32 @test_atomic_rmw_xchg_16(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_xchg_16(i32 %iptr, i32 %v) {
entry:
%trunc = trunc i32 %v to i16
%ptr = inttoptr i32 %iptr to i16*
@@ -497,7 +497,7 @@ entry:
ret i32 %a_ext
}
-; CHECK-NEXT: define i32 @test_atomic_rmw_xchg_16(i32 %iptr, i32 %v) {
+; CHECK-NEXT: define internal i32 @test_atomic_rmw_xchg_16(i32 %iptr, i32 %v) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %trunc = trunc i32 %v to i16
; CHECK-NEXT: %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 6, i32 %iptr, i16 %trunc, i32 6)
@@ -505,27 +505,27 @@ entry:
; CHECK-NEXT: ret i32 %a_ext
; CHECK-NEXT: }
-define i32 @test_atomic_rmw_xchg_32(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_xchg_32(i32 %iptr, i32 %v) {
entry:
%ptr = inttoptr i32 %iptr to i32*
%a = call i32 @llvm.nacl.atomic.rmw.i32(i32 6, i32* %ptr, i32 %v, i32 6)
ret i32 %a
}
-; CHECK-NEXT: define i32 @test_atomic_rmw_xchg_32(i32 %iptr, i32 %v) {
+; CHECK-NEXT: define internal i32 @test_atomic_rmw_xchg_32(i32 %iptr, i32 %v) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 6, i32 %iptr, i32 %v, i32 6)
; CHECK-NEXT: ret i32 %a
; CHECK-NEXT: }
-define i64 @test_atomic_rmw_xchg_64(i32 %iptr, i64 %v) {
+define internal i64 @test_atomic_rmw_xchg_64(i32 %iptr, i64 %v) {
entry:
%ptr = inttoptr i32 %iptr to i64*
%a = call i64 @llvm.nacl.atomic.rmw.i64(i32 6, i64* %ptr, i64 %v, i32 6)
ret i64 %a
}
-; CHECK-NEXT: define i64 @test_atomic_rmw_xchg_64(i32 %iptr, i64 %v) {
+; CHECK-NEXT: define internal i64 @test_atomic_rmw_xchg_64(i32 %iptr, i64 %v) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 6, i32 %iptr, i64 %v, i32 6)
; CHECK-NEXT: ret i64 %a
@@ -533,7 +533,7 @@ entry:
;;;; Cmpxchg
-define i32 @test_atomic_cmpxchg_8(i32 %iptr, i32 %expected, i32 %desired) {
+define internal i32 @test_atomic_cmpxchg_8(i32 %iptr, i32 %expected, i32 %desired) {
entry:
%trunc_exp = trunc i32 %expected to i8
%trunc_des = trunc i32 %desired to i8
@@ -544,7 +544,7 @@ entry:
ret i32 %old_ext
}
-; CHECK-NEXT: define i32 @test_atomic_cmpxchg_8(i32 %iptr, i32 %expected, i32 %desired) {
+; CHECK-NEXT: define internal i32 @test_atomic_cmpxchg_8(i32 %iptr, i32 %expected, i32 %desired) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %trunc_exp = trunc i32 %expected to i8
; CHECK-NEXT: %trunc_des = trunc i32 %desired to i8
@@ -553,7 +553,7 @@ entry:
; CHECK-NEXT: ret i32 %old_ext
; CHECK-NEXT: }
-define i32 @test_atomic_cmpxchg_16(i32 %iptr, i32 %expected, i32 %desired) {
+define internal i32 @test_atomic_cmpxchg_16(i32 %iptr, i32 %expected, i32 %desired) {
entry:
%trunc_exp = trunc i32 %expected to i16
%trunc_des = trunc i32 %desired to i16
@@ -564,7 +564,7 @@ entry:
ret i32 %old_ext
}
-; CHECK-NEXT: define i32 @test_atomic_cmpxchg_16(i32 %iptr, i32 %expected, i32 %desired) {
+; CHECK-NEXT: define internal i32 @test_atomic_cmpxchg_16(i32 %iptr, i32 %expected, i32 %desired) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %trunc_exp = trunc i32 %expected to i16
; CHECK-NEXT: %trunc_des = trunc i32 %desired to i16
@@ -573,7 +573,7 @@ entry:
; CHECK-NEXT: ret i32 %old_ext
; CHECK-NEXT: }
-define i32 @test_atomic_cmpxchg_32(i32 %iptr, i32 %expected, i32 %desired) {
+define internal i32 @test_atomic_cmpxchg_32(i32 %iptr, i32 %expected, i32 %desired) {
entry:
%ptr = inttoptr i32 %iptr to i32*
%old = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %expected,
@@ -581,13 +581,13 @@ entry:
ret i32 %old
}
-; CHECK-NEXT: define i32 @test_atomic_cmpxchg_32(i32 %iptr, i32 %expected, i32 %desired) {
+; CHECK-NEXT: define internal i32 @test_atomic_cmpxchg_32(i32 %iptr, i32 %expected, i32 %desired) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %old = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32 %iptr, i32 %expected, i32 %desired, i32 6, i32 6)
; CHECK-NEXT: ret i32 %old
; CHECK-NEXT: }
-define i64 @test_atomic_cmpxchg_64(i32 %iptr, i64 %expected, i64 %desired) {
+define internal i64 @test_atomic_cmpxchg_64(i32 %iptr, i64 %expected, i64 %desired) {
entry:
%ptr = inttoptr i32 %iptr to i64*
%old = call i64 @llvm.nacl.atomic.cmpxchg.i64(i64* %ptr, i64 %expected,
@@ -595,7 +595,7 @@ entry:
ret i64 %old
}
-; CHECK-NEXT: define i64 @test_atomic_cmpxchg_64(i32 %iptr, i64 %expected, i64 %desired) {
+; CHECK-NEXT: define internal i64 @test_atomic_cmpxchg_64(i32 %iptr, i64 %expected, i64 %desired) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %old = call i64 @llvm.nacl.atomic.cmpxchg.i64(i32 %iptr, i64 %expected, i64 %desired, i32 6, i32 6)
; CHECK-NEXT: ret i64 %old
@@ -603,31 +603,31 @@ entry:
;;;; Fence and is-lock-free.
-define void @test_atomic_fence() {
+define internal void @test_atomic_fence() {
entry:
call void @llvm.nacl.atomic.fence(i32 6)
ret void
}
-; CHECK-NEXT: define void @test_atomic_fence() {
+; CHECK-NEXT: define internal void @test_atomic_fence() {
; CHECK-NEXT: entry:
; CHECK-NEXT: call void @llvm.nacl.atomic.fence(i32 6)
; CHECK-NEXT: ret void
; CHECK-NEXT: }
-define void @test_atomic_fence_all() {
+define internal void @test_atomic_fence_all() {
entry:
call void @llvm.nacl.atomic.fence.all()
ret void
}
-; CHECK-NEXT: define void @test_atomic_fence_all() {
+; CHECK-NEXT: define internal void @test_atomic_fence_all() {
; CHECK-NEXT: entry:
; CHECK-NEXT: call void @llvm.nacl.atomic.fence.all()
; CHECK-NEXT: ret void
; CHECK-NEXT: }
-define i32 @test_atomic_is_lock_free(i32 %iptr) {
+define internal i32 @test_atomic_is_lock_free(i32 %iptr) {
entry:
%ptr = inttoptr i32 %iptr to i8*
%i = call i1 @llvm.nacl.atomic.is.lock.free(i32 4, i8* %ptr)
@@ -635,7 +635,7 @@ entry:
ret i32 %r
}
-; CHECK-NEXT: define i32 @test_atomic_is_lock_free(i32 %iptr) {
+; CHECK-NEXT: define internal i32 @test_atomic_is_lock_free(i32 %iptr) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %i = call i1 @llvm.nacl.atomic.is.lock.free(i32 4, i32 %iptr)
; CHECK-NEXT: %r = zext i1 %i to i32
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