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Unified Diff: tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll

Issue 1387963002: Make sure that all globals are internal, except for "start" functions. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fix nit. Created 5 years, 2 months ago
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Index: tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll
diff --git a/tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll b/tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll
index d353c9687c2442df3b7411d44f086dcdc6ed9c9e..22522a6ce265550afabbd6ce9ee78fc50c4455a4 100644
--- a/tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll
+++ b/tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll
@@ -2,11 +2,11 @@
; size allowed.
; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
-; RUN: | FileCheck %s
+; RUN: -allow-externally-defined-symbols | FileCheck %s
; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
-; RUN: | FileCheck --check-prefix=O2 %s
+; RUN: -allow-externally-defined-symbols | FileCheck --check-prefix=O2 %s
; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \
-; RUN: | FileCheck %s
+; RUN: -allow-externally-defined-symbols | FileCheck %s
declare i8 @llvm.nacl.atomic.load.i8(i8*, i32)
declare i16 @llvm.nacl.atomic.load.i16(i16*, i32)
@@ -43,7 +43,7 @@ declare i1 @llvm.nacl.atomic.is.lock.free(i32, i8*)
; x86 guarantees load/store to be atomic if naturally aligned.
; The PNaCl IR requires all atomic accesses to be naturally aligned.
-define i32 @test_atomic_load_8(i32 %iptr) {
+define internal i32 @test_atomic_load_8(i32 %iptr) {
entry:
%ptr = inttoptr i32 %iptr to i8*
; parameter value "6" is for the sequential consistency memory order.
@@ -56,7 +56,7 @@ entry:
; CHECK: mov {{.*}},DWORD
; CHECK: mov {{.*}},BYTE
-define i32 @test_atomic_load_16(i32 %iptr) {
+define internal i32 @test_atomic_load_16(i32 %iptr) {
entry:
%ptr = inttoptr i32 %iptr to i16*
%i = call i16 @llvm.nacl.atomic.load.i16(i16* %ptr, i32 6)
@@ -68,7 +68,7 @@ entry:
; CHECK: mov {{.*}},DWORD
; CHECK: mov {{.*}},WORD
-define i32 @test_atomic_load_32(i32 %iptr) {
+define internal i32 @test_atomic_load_32(i32 %iptr) {
entry:
%ptr = inttoptr i32 %iptr to i32*
%r = call i32 @llvm.nacl.atomic.load.i32(i32* %ptr, i32 6)
@@ -78,7 +78,7 @@ entry:
; CHECK: mov {{.*}},DWORD
; CHECK: mov {{.*}},DWORD
-define i64 @test_atomic_load_64(i32 %iptr) {
+define internal i64 @test_atomic_load_64(i32 %iptr) {
entry:
%ptr = inttoptr i32 %iptr to i64*
%r = call i64 @llvm.nacl.atomic.load.i64(i64* %ptr, i32 6)
@@ -88,7 +88,7 @@ entry:
; CHECK: movq x{{.*}},QWORD
; CHECK: movq QWORD {{.*}},x{{.*}}
-define i32 @test_atomic_load_32_with_arith(i32 %iptr) {
+define internal i32 @test_atomic_load_32_with_arith(i32 %iptr) {
entry:
br label %next
@@ -107,7 +107,7 @@ next:
; O2: mov {{.*}},DWORD
; O2: sub {{.*}},DWORD
-define i32 @test_atomic_load_32_ignored(i32 %iptr) {
+define internal i32 @test_atomic_load_32_ignored(i32 %iptr) {
entry:
%ptr = inttoptr i32 %iptr to i32*
%ignored = call i32 @llvm.nacl.atomic.load.i32(i32* %ptr, i32 6)
@@ -120,7 +120,7 @@ entry:
; O2: mov {{.*}},DWORD
; O2: mov {{.*}},DWORD
-define i64 @test_atomic_load_64_ignored(i32 %iptr) {
+define internal i64 @test_atomic_load_64_ignored(i32 %iptr) {
entry:
%ptr = inttoptr i32 %iptr to i64*
%ignored = call i64 @llvm.nacl.atomic.load.i64(i64* %ptr, i32 6)
@@ -132,7 +132,7 @@ entry:
;;; Store
-define void @test_atomic_store_8(i32 %iptr, i32 %v) {
+define internal void @test_atomic_store_8(i32 %iptr, i32 %v) {
entry:
%truncv = trunc i32 %v to i8
%ptr = inttoptr i32 %iptr to i8*
@@ -143,7 +143,7 @@ entry:
; CHECK: mov BYTE
; CHECK: mfence
-define void @test_atomic_store_16(i32 %iptr, i32 %v) {
+define internal void @test_atomic_store_16(i32 %iptr, i32 %v) {
entry:
%truncv = trunc i32 %v to i16
%ptr = inttoptr i32 %iptr to i16*
@@ -154,7 +154,7 @@ entry:
; CHECK: mov WORD
; CHECK: mfence
-define void @test_atomic_store_32(i32 %iptr, i32 %v) {
+define internal void @test_atomic_store_32(i32 %iptr, i32 %v) {
entry:
%ptr = inttoptr i32 %iptr to i32*
call void @llvm.nacl.atomic.store.i32(i32 %v, i32* %ptr, i32 6)
@@ -164,7 +164,7 @@ entry:
; CHECK: mov DWORD
; CHECK: mfence
-define void @test_atomic_store_64(i32 %iptr, i64 %v) {
+define internal void @test_atomic_store_64(i32 %iptr, i64 %v) {
entry:
%ptr = inttoptr i32 %iptr to i64*
call void @llvm.nacl.atomic.store.i64(i64 %v, i64* %ptr, i32 6)
@@ -175,7 +175,7 @@ entry:
; CHECK: movq QWORD {{.*}},x{{.*}}
; CHECK: mfence
-define void @test_atomic_store_64_const(i32 %iptr) {
+define internal void @test_atomic_store_64_const(i32 %iptr) {
entry:
%ptr = inttoptr i32 %iptr to i64*
call void @llvm.nacl.atomic.store.i64(i64 12345678901234, i64* %ptr, i32 6)
@@ -193,7 +193,7 @@ entry:
;; add
-define i32 @test_atomic_rmw_add_8(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_add_8(i32 %iptr, i32 %v) {
entry:
%trunc = trunc i32 %v to i8
%ptr = inttoptr i32 %iptr to i8*
@@ -206,7 +206,7 @@ entry:
; CHECK: lock xadd BYTE {{.*}},[[REG:.*]]
; CHECK: {{mov|movzx}} {{.*}},[[REG]]
-define i32 @test_atomic_rmw_add_16(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_add_16(i32 %iptr, i32 %v) {
entry:
%trunc = trunc i32 %v to i16
%ptr = inttoptr i32 %iptr to i16*
@@ -218,7 +218,7 @@ entry:
; CHECK: lock xadd WORD {{.*}},[[REG:.*]]
; CHECK: {{mov|movzx}} {{.*}},[[REG]]
-define i32 @test_atomic_rmw_add_32(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_add_32(i32 %iptr, i32 %v) {
entry:
%ptr = inttoptr i32 %iptr to i32*
%a = call i32 @llvm.nacl.atomic.rmw.i32(i32 1, i32* %ptr, i32 %v, i32 6)
@@ -228,7 +228,7 @@ entry:
; CHECK: lock xadd DWORD {{.*}},[[REG:.*]]
; CHECK: mov {{.*}},[[REG]]
-define i64 @test_atomic_rmw_add_64(i32 %iptr, i64 %v) {
+define internal i64 @test_atomic_rmw_add_64(i32 %iptr, i64 %v) {
entry:
%ptr = inttoptr i32 %iptr to i64*
%a = call i64 @llvm.nacl.atomic.rmw.i64(i32 1, i64* %ptr, i64 %v, i32 6)
@@ -251,7 +251,7 @@ entry:
; CHECK: jne [[LABEL]]
; Same test as above, but with a global address to test FakeUse issues.
-define i64 @test_atomic_rmw_add_64_global(i64 %v) {
+define internal i64 @test_atomic_rmw_add_64_global(i64 %v) {
entry:
%ptr = bitcast [8 x i8]* @Global64 to i64*
%a = call i64 @llvm.nacl.atomic.rmw.i64(i32 1, i64* %ptr, i64 %v, i32 6)
@@ -263,7 +263,7 @@ entry:
; used to manage the stack frame, so it cannot be used as a register either.
declare void @use_ptr(i32 %iptr)
-define i64 @test_atomic_rmw_add_64_alloca(i32 %iptr, i64 %v) {
+define internal i64 @test_atomic_rmw_add_64_alloca(i32 %iptr, i64 %v) {
entry:
br label %eblock ; Disable alloca optimization
eblock:
@@ -292,7 +292,7 @@ eblock:
; CHECK: lock cmpxchg8b QWORD PTR [e{{[ds]}}i]
; CHECK: call {{.*}} R_{{.*}} use_ptr
-define i32 @test_atomic_rmw_add_32_ignored(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_add_32_ignored(i32 %iptr, i32 %v) {
entry:
%ptr = inttoptr i32 %iptr to i32*
%ignored = call i32 @llvm.nacl.atomic.rmw.i32(i32 1, i32* %ptr, i32 %v, i32 6)
@@ -305,7 +305,7 @@ entry:
; Atomic RMW 64 needs to be expanded into its own loop.
; Make sure that works w/ non-trivial function bodies.
-define i64 @test_atomic_rmw_add_64_loop(i32 %iptr, i64 %v) {
+define internal i64 @test_atomic_rmw_add_64_loop(i32 %iptr, i64 %v) {
entry:
%x = icmp ult i64 %v, 100
br i1 %x, label %err, label %loop
@@ -336,7 +336,7 @@ err:
;; sub
-define i32 @test_atomic_rmw_sub_8(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_sub_8(i32 %iptr, i32 %v) {
entry:
%trunc = trunc i32 %v to i8
%ptr = inttoptr i32 %iptr to i8*
@@ -349,7 +349,7 @@ entry:
; CHECK: lock xadd BYTE {{.*}},[[REG]]
; CHECK: {{mov|movzx}} {{.*}},[[REG]]
-define i32 @test_atomic_rmw_sub_16(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_sub_16(i32 %iptr, i32 %v) {
entry:
%trunc = trunc i32 %v to i16
%ptr = inttoptr i32 %iptr to i16*
@@ -362,7 +362,7 @@ entry:
; CHECK: lock xadd WORD {{.*}},[[REG]]
; CHECK: {{mov|movzx}} {{.*}},[[REG]]
-define i32 @test_atomic_rmw_sub_32(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_sub_32(i32 %iptr, i32 %v) {
entry:
%ptr = inttoptr i32 %iptr to i32*
%a = call i32 @llvm.nacl.atomic.rmw.i32(i32 2, i32* %ptr, i32 %v, i32 6)
@@ -373,7 +373,7 @@ entry:
; CHECK: lock xadd DWORD {{.*}},[[REG]]
; CHECK: mov {{.*}},[[REG]]
-define i64 @test_atomic_rmw_sub_64(i32 %iptr, i64 %v) {
+define internal i64 @test_atomic_rmw_sub_64(i32 %iptr, i64 %v) {
entry:
%ptr = inttoptr i32 %iptr to i64*
%a = call i64 @llvm.nacl.atomic.rmw.i64(i32 2, i64* %ptr, i64 %v, i32 6)
@@ -391,7 +391,7 @@ entry:
; CHECK: jne [[LABEL]]
-define i32 @test_atomic_rmw_sub_32_ignored(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_sub_32_ignored(i32 %iptr, i32 %v) {
entry:
%ptr = inttoptr i32 %iptr to i32*
%ignored = call i32 @llvm.nacl.atomic.rmw.i32(i32 2, i32* %ptr, i32 %v, i32 6)
@@ -404,7 +404,7 @@ entry:
;; or
-define i32 @test_atomic_rmw_or_8(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_or_8(i32 %iptr, i32 %v) {
entry:
%trunc = trunc i32 %v to i8
%ptr = inttoptr i32 %iptr to i8*
@@ -421,7 +421,7 @@ entry:
; CHECK: jne
; Same test as above, but with a global address to test FakeUse issues.
-define i32 @test_atomic_rmw_or_8_global(i32 %v) {
+define internal i32 @test_atomic_rmw_or_8_global(i32 %v) {
entry:
%trunc = trunc i32 %v to i8
%ptr = bitcast [1 x i8]* @Global8 to i8*
@@ -431,7 +431,7 @@ entry:
}
; CHECK-LABEL: test_atomic_rmw_or_8_global
-define i32 @test_atomic_rmw_or_16(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_or_16(i32 %iptr, i32 %v) {
entry:
%trunc = trunc i32 %v to i16
%ptr = inttoptr i32 %iptr to i16*
@@ -446,7 +446,7 @@ entry:
; CHECK: jne
; Same test as above, but with a global address to test FakeUse issues.
-define i32 @test_atomic_rmw_or_16_global(i32 %v) {
+define internal i32 @test_atomic_rmw_or_16_global(i32 %v) {
entry:
%trunc = trunc i32 %v to i16
%ptr = bitcast [2 x i8]* @Global16 to i16*
@@ -456,7 +456,7 @@ entry:
}
; CHECK-LABEL: test_atomic_rmw_or_16_global
-define i32 @test_atomic_rmw_or_32(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_or_32(i32 %iptr, i32 %v) {
entry:
%ptr = inttoptr i32 %iptr to i32*
%a = call i32 @llvm.nacl.atomic.rmw.i32(i32 3, i32* %ptr, i32 %v, i32 6)
@@ -469,7 +469,7 @@ entry:
; CHECK: jne
; Same test as above, but with a global address to test FakeUse issues.
-define i32 @test_atomic_rmw_or_32_global(i32 %v) {
+define internal i32 @test_atomic_rmw_or_32_global(i32 %v) {
entry:
%ptr = bitcast [4 x i8]* @Global32 to i32*
%a = call i32 @llvm.nacl.atomic.rmw.i32(i32 3, i32* %ptr, i32 %v, i32 6)
@@ -477,7 +477,7 @@ entry:
}
; CHECK-LABEL: test_atomic_rmw_or_32_global
-define i64 @test_atomic_rmw_or_64(i32 %iptr, i64 %v) {
+define internal i64 @test_atomic_rmw_or_64(i32 %iptr, i64 %v) {
entry:
%ptr = inttoptr i32 %iptr to i64*
%a = call i64 @llvm.nacl.atomic.rmw.i64(i32 3, i64* %ptr, i64 %v, i32 6)
@@ -494,7 +494,7 @@ entry:
; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}
; CHECK: jne [[LABEL]]
-define i32 @test_atomic_rmw_or_32_ignored(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_or_32_ignored(i32 %iptr, i32 %v) {
entry:
%ptr = inttoptr i32 %iptr to i32*
%ignored = call i32 @llvm.nacl.atomic.rmw.i32(i32 3, i32* %ptr, i32 %v, i32 6)
@@ -511,7 +511,7 @@ entry:
;; and
-define i32 @test_atomic_rmw_and_8(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_and_8(i32 %iptr, i32 %v) {
entry:
%trunc = trunc i32 %v to i8
%ptr = inttoptr i32 %iptr to i8*
@@ -525,7 +525,7 @@ entry:
; CHECK: lock cmpxchg BYTE PTR [e{{[^a].}}],[[REG]]
; CHECK: jne
-define i32 @test_atomic_rmw_and_16(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_and_16(i32 %iptr, i32 %v) {
entry:
%trunc = trunc i32 %v to i16
%ptr = inttoptr i32 %iptr to i16*
@@ -539,7 +539,7 @@ entry:
; CHECK: lock cmpxchg WORD PTR [e{{[^a].}}]
; CHECK: jne
-define i32 @test_atomic_rmw_and_32(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_and_32(i32 %iptr, i32 %v) {
entry:
%ptr = inttoptr i32 %iptr to i32*
%a = call i32 @llvm.nacl.atomic.rmw.i32(i32 4, i32* %ptr, i32 %v, i32 6)
@@ -551,7 +551,7 @@ entry:
; CHECK: lock cmpxchg DWORD PTR [e{{[^a].}}]
; CHECK: jne
-define i64 @test_atomic_rmw_and_64(i32 %iptr, i64 %v) {
+define internal i64 @test_atomic_rmw_and_64(i32 %iptr, i64 %v) {
entry:
%ptr = inttoptr i32 %iptr to i64*
%a = call i64 @llvm.nacl.atomic.rmw.i64(i32 4, i64* %ptr, i64 %v, i32 6)
@@ -568,7 +568,7 @@ entry:
; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}
; CHECK: jne [[LABEL]]
-define i32 @test_atomic_rmw_and_32_ignored(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_and_32_ignored(i32 %iptr, i32 %v) {
entry:
%ptr = inttoptr i32 %iptr to i32*
%ignored = call i32 @llvm.nacl.atomic.rmw.i32(i32 4, i32* %ptr, i32 %v, i32 6)
@@ -583,7 +583,7 @@ entry:
;; xor
-define i32 @test_atomic_rmw_xor_8(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_xor_8(i32 %iptr, i32 %v) {
entry:
%trunc = trunc i32 %v to i8
%ptr = inttoptr i32 %iptr to i8*
@@ -597,7 +597,7 @@ entry:
; CHECK: lock cmpxchg BYTE PTR [e{{[^a].}}],[[REG]]
; CHECK: jne
-define i32 @test_atomic_rmw_xor_16(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_xor_16(i32 %iptr, i32 %v) {
entry:
%trunc = trunc i32 %v to i16
%ptr = inttoptr i32 %iptr to i16*
@@ -612,7 +612,7 @@ entry:
; CHECK: jne
-define i32 @test_atomic_rmw_xor_32(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_xor_32(i32 %iptr, i32 %v) {
entry:
%ptr = inttoptr i32 %iptr to i32*
%a = call i32 @llvm.nacl.atomic.rmw.i32(i32 5, i32* %ptr, i32 %v, i32 6)
@@ -624,7 +624,7 @@ entry:
; CHECK: lock cmpxchg DWORD PTR [e{{[^a].}}]
; CHECK: jne
-define i64 @test_atomic_rmw_xor_64(i32 %iptr, i64 %v) {
+define internal i64 @test_atomic_rmw_xor_64(i32 %iptr, i64 %v) {
entry:
%ptr = inttoptr i32 %iptr to i64*
%a = call i64 @llvm.nacl.atomic.rmw.i64(i32 5, i64* %ptr, i64 %v, i32 6)
@@ -641,7 +641,7 @@ entry:
; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}
; CHECK: jne
-define i32 @test_atomic_rmw_xor_32_ignored(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_xor_32_ignored(i32 %iptr, i32 %v) {
entry:
%ptr = inttoptr i32 %iptr to i32*
%ignored = call i32 @llvm.nacl.atomic.rmw.i32(i32 5, i32* %ptr, i32 %v, i32 6)
@@ -655,7 +655,7 @@ entry:
;; exchange
-define i32 @test_atomic_rmw_xchg_8(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_xchg_8(i32 %iptr, i32 %v) {
entry:
%trunc = trunc i32 %v to i8
%ptr = inttoptr i32 %iptr to i8*
@@ -666,7 +666,7 @@ entry:
; CHECK-LABEL: test_atomic_rmw_xchg_8
; CHECK: xchg BYTE PTR {{.*}},[[REG:.*]]
-define i32 @test_atomic_rmw_xchg_16(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_xchg_16(i32 %iptr, i32 %v) {
entry:
%trunc = trunc i32 %v to i16
%ptr = inttoptr i32 %iptr to i16*
@@ -677,7 +677,7 @@ entry:
; CHECK-LABEL: test_atomic_rmw_xchg_16
; CHECK: xchg WORD PTR {{.*}},[[REG:.*]]
-define i32 @test_atomic_rmw_xchg_32(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_xchg_32(i32 %iptr, i32 %v) {
entry:
%ptr = inttoptr i32 %iptr to i32*
%a = call i32 @llvm.nacl.atomic.rmw.i32(i32 6, i32* %ptr, i32 %v, i32 6)
@@ -686,7 +686,7 @@ entry:
; CHECK-LABEL: test_atomic_rmw_xchg_32
; CHECK: xchg DWORD PTR {{.*}},[[REG:.*]]
-define i64 @test_atomic_rmw_xchg_64(i32 %iptr, i64 %v) {
+define internal i64 @test_atomic_rmw_xchg_64(i32 %iptr, i64 %v) {
entry:
%ptr = inttoptr i32 %iptr to i64*
%a = call i64 @llvm.nacl.atomic.rmw.i64(i32 6, i64* %ptr, i64 %v, i32 6)
@@ -701,7 +701,7 @@ entry:
; CHECK: lock cmpxchg8b QWORD PTR [{{e.[^x]}}
; CHECK: jne
-define i32 @test_atomic_rmw_xchg_32_ignored(i32 %iptr, i32 %v) {
+define internal i32 @test_atomic_rmw_xchg_32_ignored(i32 %iptr, i32 %v) {
entry:
%ptr = inttoptr i32 %iptr to i32*
%ignored = call i32 @llvm.nacl.atomic.rmw.i32(i32 6, i32* %ptr, i32 %v, i32 6)
@@ -714,7 +714,8 @@ entry:
;;;; Cmpxchg
-define i32 @test_atomic_cmpxchg_8(i32 %iptr, i32 %expected, i32 %desired) {
+define internal i32 @test_atomic_cmpxchg_8(i32 %iptr, i32 %expected,
+ i32 %desired) {
entry:
%trunc_exp = trunc i32 %expected to i8
%trunc_des = trunc i32 %desired to i8
@@ -730,7 +731,8 @@ entry:
; since it is already used as the *expected* register.
; CHECK: lock cmpxchg BYTE PTR [e{{[^a].}}],{{[^a]}}l
-define i32 @test_atomic_cmpxchg_16(i32 %iptr, i32 %expected, i32 %desired) {
+define internal i32 @test_atomic_cmpxchg_16(i32 %iptr, i32 %expected,
+ i32 %desired) {
entry:
%trunc_exp = trunc i32 %expected to i16
%trunc_des = trunc i32 %desired to i16
@@ -744,7 +746,8 @@ entry:
; CHECK: mov eax,{{.*}}
; CHECK: lock cmpxchg WORD PTR [e{{[^a].}}],{{[^a]}}x
-define i32 @test_atomic_cmpxchg_32(i32 %iptr, i32 %expected, i32 %desired) {
+define internal i32 @test_atomic_cmpxchg_32(i32 %iptr, i32 %expected,
+ i32 %desired) {
entry:
%ptr = inttoptr i32 %iptr to i32*
%old = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %expected,
@@ -755,7 +758,8 @@ entry:
; CHECK: mov eax,{{.*}}
; CHECK: lock cmpxchg DWORD PTR [e{{[^a].}}],e{{[^a]}}
-define i64 @test_atomic_cmpxchg_64(i32 %iptr, i64 %expected, i64 %desired) {
+define internal i64 @test_atomic_cmpxchg_64(i32 %iptr, i64 %expected,
+ i64 %desired) {
entry:
%ptr = inttoptr i32 %iptr to i64*
%old = call i64 @llvm.nacl.atomic.cmpxchg.i64(i64* %ptr, i64 %expected,
@@ -773,7 +777,7 @@ entry:
; need to be reshuffled via movs. The next test stores the result
; somewhere, so in that case they do need to be mov'ed.
-define i64 @test_atomic_cmpxchg_64_undef(i32 %iptr, i64 %desired) {
+define internal i64 @test_atomic_cmpxchg_64_undef(i32 %iptr, i64 %desired) {
entry:
%ptr = inttoptr i32 %iptr to i64*
%old = call i64 @llvm.nacl.atomic.cmpxchg.i64(i64* %ptr, i64 undef,
@@ -784,7 +788,8 @@ entry:
; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}+0x0]
; Test a case where %old really does need to be copied out of edx:eax.
-define void @test_atomic_cmpxchg_64_store(i32 %ret_iptr, i32 %iptr, i64 %expected, i64 %desired) {
+define internal void @test_atomic_cmpxchg_64_store(
+ i32 %ret_iptr, i32 %iptr, i64 %expected, i64 %desired) {
entry:
%ptr = inttoptr i32 %iptr to i64*
%old = call i64 @llvm.nacl.atomic.cmpxchg.i64(i64* %ptr, i64 %expected,
@@ -805,7 +810,8 @@ entry:
; Test with some more register pressure. When we have an alloca, ebp is
; used to manage the stack frame, so it cannot be used as a register either.
-define i64 @test_atomic_cmpxchg_64_alloca(i32 %iptr, i64 %expected, i64 %desired) {
+define internal i64 @test_atomic_cmpxchg_64_alloca(i32 %iptr, i64 %expected,
+ i64 %desired) {
entry:
br label %eblock ; Disable alloca optimization
eblock:
@@ -835,7 +841,8 @@ eblock:
; CHECK: lock cmpxchg8b QWORD PTR [e{{[ds]}}i]
; CHECK: call {{.*}} R_{{.*}} use_ptr
-define i32 @test_atomic_cmpxchg_32_ignored(i32 %iptr, i32 %expected, i32 %desired) {
+define internal i32 @test_atomic_cmpxchg_32_ignored(i32 %iptr, i32 %expected,
+ i32 %desired) {
entry:
%ptr = inttoptr i32 %iptr to i32*
%ignored = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %expected,
@@ -846,7 +853,8 @@ entry:
; CHECK: mov eax,{{.*}}
; CHECK: lock cmpxchg DWORD PTR [e{{[^a].}}]
-define i64 @test_atomic_cmpxchg_64_ignored(i32 %iptr, i64 %expected, i64 %desired) {
+define internal i64 @test_atomic_cmpxchg_64_ignored(i32 %iptr, i64 %expected,
+ i64 %desired) {
entry:
%ptr = inttoptr i32 %iptr to i64*
%ignored = call i64 @llvm.nacl.atomic.cmpxchg.i64(i64* %ptr, i64 %expected,
@@ -863,7 +871,7 @@ entry:
;;;; Fence and is-lock-free.
-define void @test_atomic_fence() {
+define internal void @test_atomic_fence() {
entry:
call void @llvm.nacl.atomic.fence(i32 6)
ret void
@@ -871,7 +879,7 @@ entry:
; CHECK-LABEL: test_atomic_fence
; CHECK: mfence
-define void @test_atomic_fence_all() {
+define internal void @test_atomic_fence_all() {
entry:
call void @llvm.nacl.atomic.fence.all()
ret void
@@ -879,7 +887,7 @@ entry:
; CHECK-LABEL: test_atomic_fence_all
; CHECK: mfence
-define i32 @test_atomic_is_lock_free(i32 %iptr) {
+define internal i32 @test_atomic_is_lock_free(i32 %iptr) {
entry:
%ptr = inttoptr i32 %iptr to i8*
%i = call i1 @llvm.nacl.atomic.is.lock.free(i32 4, i8* %ptr)
@@ -889,7 +897,7 @@ entry:
; CHECK-LABEL: test_atomic_is_lock_free
; CHECK: mov {{.*}},0x1
-define i32 @test_not_lock_free(i32 %iptr) {
+define internal i32 @test_not_lock_free(i32 %iptr) {
entry:
%ptr = inttoptr i32 %iptr to i8*
%i = call i1 @llvm.nacl.atomic.is.lock.free(i32 7, i8* %ptr)
@@ -899,7 +907,7 @@ entry:
; CHECK-LABEL: test_not_lock_free
; CHECK: mov {{.*}},0x0
-define i32 @test_atomic_is_lock_free_ignored(i32 %iptr) {
+define internal i32 @test_atomic_is_lock_free_ignored(i32 %iptr) {
entry:
%ptr = inttoptr i32 %iptr to i8*
%ignored = call i1 @llvm.nacl.atomic.is.lock.free(i32 4, i8* %ptr)
@@ -916,7 +924,8 @@ entry:
; fact that nacl.atomic.is.lock.free will resolve to a constant
; (which adds DCE opportunities). Once we optimize, the test expectations
; for this case should change.
-define i32 @test_atomic_is_lock_free_can_dce(i32 %iptr, i32 %x, i32 %y) {
+define internal i32 @test_atomic_is_lock_free_can_dce(i32 %iptr, i32 %x,
+ i32 %y) {
entry:
%ptr = inttoptr i32 %iptr to i8*
%i = call i1 @llvm.nacl.atomic.is.lock.free(i32 4, i8* %ptr)
@@ -940,7 +949,7 @@ not_lock_free:
; Make sure we model that the Src register is modified and therefore it can't
; share a register with an overlapping live range, even if the result of the
; xadd instruction is unused.
-define void @test_xadd_regalloc() {
+define internal void @test_xadd_regalloc() {
entry:
br label %body
body:
@@ -961,7 +970,7 @@ done:
; O2: ret
; Do the same test for the xchg instruction instead of xadd.
-define void @test_xchg_regalloc() {
+define internal void @test_xchg_regalloc() {
entry:
br label %body
body:
@@ -982,7 +991,7 @@ done:
; O2: ret
; Same test for cmpxchg.
-define void @test_cmpxchg_regalloc() {
+define internal void @test_cmpxchg_regalloc() {
entry:
br label %body
body:
@@ -1003,7 +1012,7 @@ done:
; O2: ret
; Same test for cmpxchg8b.
-define void @test_cmpxchg8b_regalloc() {
+define internal void @test_cmpxchg8b_regalloc() {
entry:
br label %body
body:
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