Subzero. Adds ldrex, strex, and dmb support (ARM32)

src/IceInstARM32.h

 //===- subzero/src/IceInstARM32.h - ARM32 machine instructions --*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 273 matching lines @@
     Adc,
     Add,
     Adjuststack,
     And,
     Asr,
     Bic,
     Br,
     Call,
     Cmp,
     Clz,
+    Dmb,
     Eor,
     Label,
     Ldr,
+    Ldrex,
     Lsl,
     Lsr,
     Mla,
     Mls,
     Mov,
     Movt,
     Movw,
     Mul,
     Mvn,
     Orr,
     Pop,
     Push,
     Rbit,
     Ret,
     Rev,
     Rsb,
     Sbc,
     Sdiv,
     Str,
+    Strex,
     Sub,
     Sxt,
     Trap,
     Tst,
     Udiv,
     Umull,
     Uxt,
     Vabs,
     Vadd,
     Vcmp,
@@ skipping 192 matching lines @@
   InstARM32TwoAddrGPR(Cfg *Func, Variable *Dest, Operand *Src,
                       CondARM32::Cond Predicate)
       : InstARM32Pred(Func, K, 2, Dest, Predicate) {
     addSource(Dest);
     addSource(Src);
   }
 
   static const char *Opcode;
 };
 
-/// Base class for assignment instructions. These can be tested for redundancy
-/// (and elided if redundant).
+/// Base class for load instructions.
 template <InstARM32::InstKindARM32 K>
-class InstARM32Movlike : public InstARM32Pred {
-  InstARM32Movlike() = delete;
-  InstARM32Movlike(const InstARM32Movlike &) = delete;
-  InstARM32Movlike &operator=(const InstARM32Movlike &) = delete;
+class InstARM32LoadBase : public InstARM32Pred {
+  InstARM32LoadBase() = delete;
+  InstARM32LoadBase(const InstARM32LoadBase &) = delete;
+  InstARM32LoadBase &operator=(const InstARM32LoadBase &) = delete;
 
 public:
-  static InstARM32Movlike *create(Cfg *Func, Variable *Dest, Operand *Source,
-                                  CondARM32::Cond Predicate) {
-    return new (Func->allocate<InstARM32Movlike>())
-        InstARM32Movlike(Func, Dest, Source, Predicate);
+  static InstARM32LoadBase *create(Cfg *Func, Variable *Dest, Operand *Source,
+                                   CondARM32::Cond Predicate) {
+    return new (Func->allocate<InstARM32LoadBase>())
+        InstARM32LoadBase(Func, Dest, Source, Predicate);
   }
-  bool isRedundantAssign() const override {
-    return checkForRedundantAssign(getDest(), getSrc(0));
-  }
-  bool isSimpleAssign() const override { return true; }
   void emit(const Cfg *Func) const override;
   void emitIAS(const Cfg *Func) const override;
   void dump(const Cfg *Func) const override {
     if (!BuildDefs::dump())
       return;
     Ostream &Str = Func->getContext()->getStrDump();
     dumpOpcodePred(Str, Opcode, getDest()->getType());
     Str << " ";
     dumpDest(Func);
     Str << ", ";
     dumpSources(Func);
   }
   static bool classof(const Inst *Inst) { return isClassof(Inst, K); }
 
 private:
-  InstARM32Movlike(Cfg *Func, Variable *Dest, Operand *Source,
-                   CondARM32::Cond Predicate)
+  InstARM32LoadBase(Cfg *Func, Variable *Dest, Operand *Source,
+                    CondARM32::Cond Predicate)
       : InstARM32Pred(Func, K, 1, Dest, Predicate) {
     addSource(Source);
   }
 
   static const char *Opcode;
 };
 
 /// Instructions of the form x := y op z. May have the side-effect of setting
 /// status flags.
 template <InstARM32::InstKindARM32 K>
@@ skipping 198 matching lines @@
 using InstARM32Orr = InstARM32ThreeAddrGPR<InstARM32::Orr>;
 using InstARM32Rsb = InstARM32ThreeAddrGPR<InstARM32::Rsb>;
 using InstARM32Sbc = InstARM32ThreeAddrGPR<InstARM32::Sbc>;
 using InstARM32Sdiv = InstARM32ThreeAddrGPR<InstARM32::Sdiv>;
 using InstARM32Sub = InstARM32ThreeAddrGPR<InstARM32::Sub>;
 using InstARM32Udiv = InstARM32ThreeAddrGPR<InstARM32::Udiv>;
 using InstARM32Vadd = InstARM32ThreeAddrFP<InstARM32::Vadd>;
 using InstARM32Vdiv = InstARM32ThreeAddrFP<InstARM32::Vdiv>;
 using InstARM32Vmul = InstARM32ThreeAddrFP<InstARM32::Vmul>;
 using InstARM32Vsub = InstARM32ThreeAddrFP<InstARM32::Vsub>;
-using InstARM32Ldr = InstARM32Movlike<InstARM32::Ldr>;
+using InstARM32Ldr = InstARM32LoadBase<InstARM32::Ldr>;
+using InstARM32Ldrex = InstARM32LoadBase<InstARM32::Ldrex>;
 /// MovT leaves the bottom bits alone so dest is also a source. This helps
 /// indicate that a previous MovW setting dest is not dead code.
 using InstARM32Movt = InstARM32TwoAddrGPR<InstARM32::Movt>;
 using InstARM32Movw = InstARM32UnaryopGPR<InstARM32::Movw, false>;
 using InstARM32Clz = InstARM32UnaryopGPR<InstARM32::Clz, false>;
 using InstARM32Mvn = InstARM32UnaryopGPR<InstARM32::Mvn, false>;
 using InstARM32Rbit = InstARM32UnaryopGPR<InstARM32::Rbit, false>;
 using InstARM32Rev = InstARM32UnaryopGPR<InstARM32::Rev, false>;
 // Technically, the uxt{b,h} and sxt{b,h} instructions have a rotation operand
 // as well (rotate source by 8, 16, 24 bits prior to extending), but we aren't
@@ skipping 221 matching lines @@
   void emitIAS(const Cfg *Func) const override;
   void dump(const Cfg *Func) const override;
   static bool classof(const Inst *Inst) { return isClassof(Inst, Ret); }
 
 private:
   InstARM32Ret(Cfg *Func, Variable *LR, Variable *Source);
 };
 
 /// Store instruction. It's important for liveness that there is no Dest operand
 /// (OperandARM32Mem instead of Dest Variable).
-class InstARM32Str : public InstARM32Pred {
+class InstARM32Str final : public InstARM32Pred {
   InstARM32Str() = delete;
   InstARM32Str(const InstARM32Str &) = delete;
   InstARM32Str &operator=(const InstARM32Str &) = delete;
 
 public:
   /// Value must be a register.
   static InstARM32Str *create(Cfg *Func, Variable *Value, OperandARM32Mem *Mem,
                               CondARM32::Cond Predicate) {
     return new (Func->allocate<InstARM32Str>())
         InstARM32Str(Func, Value, Mem, Predicate);
   }
   void emit(const Cfg *Func) const override;
   void emitIAS(const Cfg *Func) const override;
   void dump(const Cfg *Func) const override;
   static bool classof(const Inst *Inst) { return isClassof(Inst, Str); }
 
 private:
   InstARM32Str(Cfg *Func, Variable *Value, OperandARM32Mem *Mem,
                CondARM32::Cond Predicate);
 };
 
+/// Exclusive Store instruction. Like its non-exclusive sibling, it's important
+/// for liveness that there is no Dest operand (OperandARM32Mem instead of Dest
+/// Variable).
+class InstARM32Strex final : public InstARM32Pred {
+  InstARM32Strex() = delete;
+  InstARM32Strex(const InstARM32Strex &) = delete;
+  InstARM32Strex &operator=(const InstARM32Strex &) = delete;
+
+public:
+  /// Value must be a register.
+  static InstARM32Strex *create(Cfg *Func, Variable *Dest, Variable *Value,
+                                OperandARM32Mem *Mem,
+                                CondARM32::Cond Predicate) {
+    return new (Func->allocate<InstARM32Strex>())
+        InstARM32Strex(Func, Dest, Value, Mem, Predicate);
+  }
+  void emit(const Cfg *Func) const override;
+  void emitIAS(const Cfg *Func) const override;
+  void dump(const Cfg *Func) const override;
+  static bool classof(const Inst *Inst) { return isClassof(Inst, Strex); }
+
+private:
+  InstARM32Strex(Cfg *Func, Variable *Dest, Variable *Value,
+                 OperandARM32Mem *Mem, CondARM32::Cond Predicate);
+};
+
 class InstARM32Trap : public InstARM32 {
   InstARM32Trap() = delete;
   InstARM32Trap(const InstARM32Trap &) = delete;
   InstARM32Trap &operator=(const InstARM32Trap &) = delete;
 
 public:
   static InstARM32Trap *create(Cfg *Func) {
     return new (Func->allocate<InstARM32Trap>()) InstARM32Trap(Func);
   }
   void emit(const Cfg *Func) const override;
@@ skipping 151 matching lines @@
   }
   void emit(const Cfg *Func) const override;
   void emitIAS(const Cfg *Func) const override;
   void dump(const Cfg *Func) const override;
   static bool classof(const Inst *Inst) { return isClassof(Inst, Vabs); }
 
 private:
   InstARM32Vabs(Cfg *Func, Variable *Dest, Variable *Src,
                 CondARM32::Cond Predicate);
 };
+
+class InstARM32Dmb final : public InstARM32Pred {
+  InstARM32Dmb() = delete;
+  InstARM32Dmb(const InstARM32Dmb &) = delete;
+  InstARM32Dmb &operator=(const InstARM32Dmb &) = delete;
+
+public:
+  static InstARM32Dmb *create(Cfg *Func) {
+    return new (Func->allocate<InstARM32Dmb>()) InstARM32Dmb(Func);
+  }
+  void emit(const Cfg *Func) const override;
+  void emitIAS(const Cfg *Func) const override;
+  void dump(const Cfg *Func) const override;
+  static bool classof(const Inst *Inst) { return isClassof(Inst, Dmb); }
+
+private:
+  explicit InstARM32Dmb(Cfg *Func);
+};
+
 // Declare partial template specializations of emit() methods that already have
 // default implementations. Without this, there is the possibility of ODR
 // violations and link errors.
 
 template <> void InstARM32Ldr::emit(const Cfg *Func) const;
 template <> void InstARM32Movw::emit(const Cfg *Func) const;
 template <> void InstARM32Movt::emit(const Cfg *Func) const;
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEINSTARM32_H