Subzero. Adds ldrex, strex, and dmb support (ARM32)

src/IceInstARM32.cpp

-//===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===//
+//===----------------------------------------------------------------------===//

[Jim Stichnoth, 2015/10/01 21:46:47]

Why was this changed?

[John, 2015/10/01 22:11:45]

Done.

 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// This file implements the InstARM32 and OperandARM32 classes, primarily the
@@ skipping 341 matching lines @@
     addSource(Source);
 }
 
 InstARM32Str::InstARM32Str(Cfg *Func, Variable *Value, OperandARM32Mem *Mem,
                            CondARM32::Cond Predicate)
     : InstARM32Pred(Func, InstARM32::Str, 2, nullptr, Predicate) {
   addSource(Value);
   addSource(Mem);
 }
 
+InstARM32Strex::InstARM32Strex(Cfg *Func, Variable *Dest, Variable *Value,
+                               OperandARM32Mem *Mem, CondARM32::Cond Predicate)
+    : InstARM32Pred(Func, InstARM32::Strex, 2, Dest, Predicate) {
+  addSource(Value);
+  addSource(Mem);
+}
+
 InstARM32Trap::InstARM32Trap(Cfg *Func)
     : InstARM32(Func, InstARM32::Trap, 0, nullptr) {}
 
 InstARM32Umull::InstARM32Umull(Cfg *Func, Variable *DestLo, Variable *DestHi,
                                Variable *Src0, Variable *Src1,
                                CondARM32::Cond Predicate)
     : InstARM32Pred(Func, InstARM32::Umull, 2, DestLo, Predicate),
       // DestHi is expected to have a FakeDef inserted by the lowering code.
       DestHi(DestHi) {
   addSource(Src0);
@@ skipping 37 matching lines @@
 }
 
 InstARM32Vmrs::InstARM32Vmrs(Cfg *Func, CondARM32::Cond Predicate)
     : InstARM32Pred(Func, InstARM32::Vmrs, 0, nullptr, Predicate) {}
 
 InstARM32Vabs::InstARM32Vabs(Cfg *Func, Variable *Dest, Variable *Src,
                              CondARM32::Cond Predicate)
     : InstARM32Pred(Func, InstARM32::Vabs, 1, Dest, Predicate) {
   addSource(Src);
 }
+
+InstARM32Dmb::InstARM32Dmb(Cfg *Func)
+    : InstARM32Pred(Func, InstARM32::Dmb, 0, nullptr, CondARM32::AL) {}
+
 // ======================== Dump routines ======================== //
 
 // Two-addr ops
 template <> const char *InstARM32Movt::Opcode = "movt";
 // Unary ops
 template <> const char *InstARM32Movw::Opcode = "movw";
 template <> const char *InstARM32Clz::Opcode = "clz";
 template <> const char *InstARM32Mvn::Opcode = "mvn";
 template <> const char *InstARM32Rbit::Opcode = "rbit";
 template <> const char *InstARM32Rev::Opcode = "rev";
 template <> const char *InstARM32Sxt::Opcode = "sxt"; // still requires b/h
 template <> const char *InstARM32Uxt::Opcode = "uxt"; // still requires b/h
 // FP
 template <> const char *InstARM32Vsqrt::Opcode = "vsqrt";
 // Mov-like ops
 template <> const char *InstARM32Ldr::Opcode = "ldr";
+template <> const char *InstARM32Ldrex::Opcode = "ldrex";
 // Three-addr ops
 template <> const char *InstARM32Adc::Opcode = "adc";
 template <> const char *InstARM32Add::Opcode = "add";
 template <> const char *InstARM32And::Opcode = "and";
 template <> const char *InstARM32Asr::Opcode = "asr";
 template <> const char *InstARM32Bic::Opcode = "bic";
 template <> const char *InstARM32Eor::Opcode = "eor";
 template <> const char *InstARM32Lsl::Opcode = "lsl";
 template <> const char *InstARM32Lsr::Opcode = "lsr";
 template <> const char *InstARM32Mul::Opcode = "mul";
@@ skipping 48 matching lines @@
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   Variable *Dest = getDest();
   Variable *SrcLo = llvm::cast<Variable>(getSrc(0));
   Variable *SrcHi = llvm::cast<Variable>(getSrc(1));
 
   assert(SrcHi->hasReg());
   assert(SrcLo->hasReg());
   assert(Dest->hasReg());
+  assert(getSrcSize() == 2);
 
   Str << "\t"
       << "vmov" << getPredicate() << "\t";
   Dest->emit(Func);
   Str << ", ";
   SrcLo->emit(Func);
   Str << ", ";
   SrcHi->emit(Func);
 }
 
@@ skipping 238 matching lines @@
   Str << ", ";
   getSrc(0)->emit(Func);
 }
 
 template <> void InstARM32Ldr::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 1);
   (void)Func;
   llvm_unreachable("Not yet implemented");
 }
 
+template <> void InstARM32Ldrex::emit(const Cfg *Func) const {
+  if (!BuildDefs::dump())
+    return;
+  Ostream &Str = Func->getContext()->getStrEmit();
+  assert(getSrcSize() == 1);
+  assert(getDest()->hasReg());
+  Variable *Dest = getDest();
+  Type DestTy = Dest->getType();
+  assert(isScalarIntegerType(DestTy));
+  const char *WidthString = getWidthString(DestTy);
+  Str << "\t" << Opcode << WidthString << getPredicate() << "\t";
+  getDest()->emit(Func);
+  Str << ", ";
+  getSrc(0)->emit(Func);
+}
+
+template <> void InstARM32Ldrex::emitIAS(const Cfg *Func) const {
+  assert(getSrcSize() == 1);
+  (void)Func;
+  llvm_unreachable("Not yet implemented");
+}
+
 template <> void InstARM32Movw::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 1);
   Str << "\t" << Opcode << getPredicate() << "\t";
   getDest()->emit(Func);
   Str << ", ";
   Constant *Src0 = llvm::cast<Constant>(getSrc(0));
   if (auto CR = llvm::dyn_cast<ConstantRelocatable>(Src0)) {
@@ skipping 203 matching lines @@
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   Type Ty = getSrc(0)->getType();
   dumpOpcodePred(Str, "str", Ty);
   Str << " ";
   getSrc(1)->dump(Func);
   Str << ", ";
   getSrc(0)->dump(Func);
 }
 
+void InstARM32Strex::emit(const Cfg *Func) const {
+  if (!BuildDefs::dump())
+    return;
+  assert(getSrcSize() == 2);
+  Type Ty = getSrc(0)->getType();
+  assert(isScalarIntegerType(Ty));
+  Variable *Dest = getDest();
+  Ostream &Str = Func->getContext()->getStrEmit();
+  static constexpr char Opcode[] = "strex";
+  const char *WidthString = getWidthString(Ty);
+  Str << "\t" << Opcode << WidthString << getPredicate() << "\t";
+  Dest->emit(Func);
+  Str << ", ";
+  emitSources(Func);
+}
+
+void InstARM32Strex::emitIAS(const Cfg *Func) const {
+  assert(getSrcSize() == 2);
+  (void)Func;
+  llvm_unreachable("Not yet implemented");
+}
+
+void InstARM32Strex::dump(const Cfg *Func) const {
+  if (!BuildDefs::dump())
+    return;
+  Ostream &Str = Func->getContext()->getStrDump();
+  Variable *Dest = getDest();
+  Dest->dump(Func);
+  Str << " = ";
+  Type Ty = getSrc(0)->getType();
+  dumpOpcodePred(Str, "strex", Ty);
+  Str << " ";
+  getSrc(1)->dump(Func);
+  Str << ", ";
+  getSrc(0)->dump(Func);
+}
+
 void InstARM32Trap::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 0);
   // There isn't a mnemonic for the special NaCl Trap encoding, so dump
   // the raw bytes.
   Str << "\t.long 0x";
   ARM32::AssemblerARM32 *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
   for (uint8_t I : Asm->getNonExecBundlePadding()) {
@@ skipping 178 matching lines @@
 }
 
 void InstARM32Vabs::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   dumpDest(Func);
   Str << " = vabs" << getPredicate() << getVecWidthString(getSrc(0)->getType());
 }
 
+void InstARM32Dmb::emit(const Cfg *Func) const {
+  if (!BuildDefs::dump())
+    return;
+  Ostream &Str = Func->getContext()->getStrEmit();
+  assert(getSrcSize() == 0);
+  Str << "\t"
+         "dmb"
+         "\t"
+         "sy";
+}
+
+void InstARM32Dmb::emitIAS(const Cfg *Func) const {
+  assert(getSrcSize() == 1);
+  (void)Func;
+  llvm_unreachable("Not yet implemented");
+}
+
+void InstARM32Dmb::dump(const Cfg *Func) const {
+  if (!BuildDefs::dump())
+    return;
+  Func->getContext()->getStrDump() << "dmb\tsy";
+}
+
 void OperandARM32Mem::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   Str << "[";
   getBase()->emit(Func);
   switch (getAddrMode()) {
   case PostIndex:
   case NegPostIndex:
     Str << "]";
@@ skipping 100 matching lines @@
   if (getShiftOp() != kNoShift) {
     Str << ", " << InstARM32ShiftAttributes[getShiftOp()].EmitString << " ";
     if (Func)
       getShiftAmt()->dump(Func);
     else
       getShiftAmt()->dump(Str);
   }
 }
 
 } // end of namespace Ice