ARM: Fix bugs in softfloat code path.

src/arm/macro-assembler-arm.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 690 matching lines @@
   int doubles_size = DwVfpRegister::NumAllocatableRegisters() * kDoubleSize;
   int register_offset = SafepointRegisterStackIndex(reg.code()) * kPointerSize;
   return MemOperand(sp, doubles_size + register_offset);
 }
 
 
 void MacroAssembler::Ldrd(Register dst1, Register dst2,
                           const MemOperand& src, Condition cond) {
   ASSERT(src.rm().is(no_reg));
   ASSERT(!dst1.is(lr));  // r14.
-  ASSERT_EQ(0, dst1.code() % 2);
-  ASSERT_EQ(dst1.code() + 1, dst2.code());
 
   // V8 does not use this addressing mode, so the fallback code
   // below doesn't support it yet.
   ASSERT((src.am() != PreIndex) && (src.am() != NegPreIndex));
 
   // Generate two ldr instructions if ldrd is not available.
-  if (CpuFeatures::IsSupported(ARMv7) && !predictable_code_size()) {
+  if (CpuFeatures::IsSupported(ARMv7) && !predictable_code_size() &&
+      (dst1.code() % 2 == 0) && (dst1.code() + 1 == dst2.code())) {
     CpuFeatureScope scope(this, ARMv7);
     ldrd(dst1, dst2, src, cond);
   } else {
     if ((src.am() == Offset) || (src.am() == NegOffset)) {
       MemOperand src2(src);
       src2.set_offset(src2.offset() + 4);
       if (dst1.is(src.rn())) {
         ldr(dst2, src2, cond);
         ldr(dst1, src, cond);
       } else {
@@ skipping 13 matching lines @@
       }
     }
   }
 }
 
 
 void MacroAssembler::Strd(Register src1, Register src2,
                           const MemOperand& dst, Condition cond) {
   ASSERT(dst.rm().is(no_reg));
   ASSERT(!src1.is(lr));  // r14.
-  ASSERT_EQ(0, src1.code() % 2);
-  ASSERT_EQ(src1.code() + 1, src2.code());
 
   // V8 does not use this addressing mode, so the fallback code
   // below doesn't support it yet.
   ASSERT((dst.am() != PreIndex) && (dst.am() != NegPreIndex));
 
   // Generate two str instructions if strd is not available.
-  if (CpuFeatures::IsSupported(ARMv7) && !predictable_code_size()) {
+  if (CpuFeatures::IsSupported(ARMv7) && !predictable_code_size() &&
+      (src1.code() % 2 == 0) && (src1.code() + 1 == src2.code())) {
     CpuFeatureScope scope(this, ARMv7);
     strd(src1, src2, dst, cond);
   } else {
     MemOperand dst2(dst);
     if ((dst.am() == Offset) || (dst.am() == NegOffset)) {
       dst2.set_offset(dst2.offset() + 4);
       str(src1, dst, cond);
       str(src2, dst2, cond);
     } else {  // PostIndex or NegPostIndex.
       ASSERT((dst.am() == PostIndex) || (dst.am() == NegPostIndex));
@@ skipping 1720 matching lines @@
   sub(result, result, Operand(1), SetCC);
   // If result is still negative, go to done, result fetched.
   // Else, we had an overflow and we fall through exception.
   b(mi, done);
   bind(&exception);
 }
 
 
 void MacroAssembler::ECMAConvertNumberToInt32(Register source,
                                               Register result,
+                                              Register input_low,
+                                              Register input_high,
                                               Register scratch,
-                                              Register input_high,
-                                              Register input_low,
                                               DwVfpRegister double_scratch1,
                                               DwVfpRegister double_scratch2) {
   if (CpuFeatures::IsSupported(VFP2)) {
     CpuFeatureScope scope(this, VFP2);
     vldr(double_scratch1, FieldMemOperand(source, HeapNumber::kValueOffset));
     ECMAToInt32VFP(result, double_scratch1, double_scratch2,
                    scratch, input_high, input_low);
   } else {
     Ldrd(input_low, input_high,
          FieldMemOperand(source, HeapNumber::kValueOffset));
@@ skipping 56 matching lines @@
   ASSERT(!result.is(input_high));
   ASSERT(!result.is(input_low));
   ASSERT(!scratch.is(input_high));
   ASSERT(!scratch.is(input_low));
   ASSERT(!input_high.is(input_low));
 
   Label both, out_of_range, negate, done;
 
   Ubfx(scratch, input_high,
        HeapNumber::kExponentShift, HeapNumber::kExponentBits);
-  // Load scratch with exponent - 1. This is faster than loading
-  // with exponent because Bias + 1 = 1024 which is an *ARM* immediate value.
-  sub(scratch, scratch, Operand(HeapNumber::kExponentBias + 1));
+  // Load scratch with exponent.
+  sub(scratch, scratch, Operand(HeapNumber::kExponentBias));
   // If exponent is negative, 0 < input < 1, the result is 0.
   // If exponent is greater than or equal to 84, the 32 less significant
   // bits are 0s (2^84 = 1, 52 significant bits, 32 uncoded bits),
   // the result is 0.
   // This test also catch Nan and infinities which also return 0.
-  // Compare exponent with 84 (compare exponent - 1 with 83).
-  cmp(scratch, Operand(83));
+  cmp(scratch, Operand(84));
   // We do an unsigned comparison so negative numbers are treated as big
   // positive number and the two tests above are done in one test.
   b(hs, &out_of_range);
 
-  // Load scratch with 20 - exponent (load with 19 - (exponent - 1)).
-  rsb(scratch, scratch, Operand(19), SetCC);
+  // Load scratch with 20 - exponent.
+  rsb(scratch, scratch, Operand(20), SetCC);
   b(mi, &both);
 
+  // Test 0 and -0.
+  bic(result, input_high, Operand(HeapNumber::kSignMask));
+  orr(result, result, Operand(input_low), SetCC);
+  b(eq, &done);
   // 0 <= exponent <= 20, shift only input_high.
   // Scratch contains: 20 - exponent.
   Ubfx(result, input_high,
        0, HeapNumber::kMantissaBitsInTopWord);
   // Set the implicit 1 before the mantissa part in input_high.
   orr(result, result, Operand(1 << HeapNumber::kMantissaBitsInTopWord));
   mov(result, Operand(result, LSR, scratch));
   b(&negate);
 
   bind(&both);
@@ skipping 1340 matching lines @@
 void CodePatcher::EmitCondition(Condition cond) {
   Instr instr = Assembler::instr_at(masm_.pc_);
   instr = (instr & ~kCondMask) | cond;
   masm_.emit(instr);
 }
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_ARM