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Issue 1241863002: VM: Refactor allocation stats code and remove duplicate code. (Closed) Base URL: git@github.com:dart-lang/sdk.git@master
Patch Set: addressed comments Created 5 years, 5 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/globals.h" // NOLINT 5 #include "vm/globals.h" // NOLINT
6 #if defined(TARGET_ARCH_MIPS) 6 #if defined(TARGET_ARCH_MIPS)
7 7
8 #include "vm/assembler.h" 8 #include "vm/assembler.h"
9 #include "vm/longjump.h" 9 #include "vm/longjump.h"
10 #include "vm/runtime_entry.h" 10 #include "vm/runtime_entry.h"
(...skipping 788 matching lines...) Expand 10 before | Expand all | Expand 10 after
799 lw(RA, Address(SP, 2 * kWordSize)); 799 lw(RA, Address(SP, 2 * kWordSize));
800 lw(FP, Address(SP, 1 * kWordSize)); 800 lw(FP, Address(SP, 1 * kWordSize));
801 lw(PP, Address(SP, 0 * kWordSize)); 801 lw(PP, Address(SP, 0 * kWordSize));
802 jr(ra); 802 jr(ra);
803 delay_slot()->addiu(SP, SP, Immediate(4 * kWordSize)); 803 delay_slot()->addiu(SP, SP, Immediate(4 * kWordSize));
804 } 804 }
805 805
806 806
807 void Assembler::UpdateAllocationStats(intptr_t cid, 807 void Assembler::UpdateAllocationStats(intptr_t cid,
808 Register temp_reg, 808 Register temp_reg,
809 Heap::Space space) { 809 Heap::Space space,
810 bool inline_isolate) {
810 ASSERT(!in_delay_slot_); 811 ASSERT(!in_delay_slot_);
811 ASSERT(temp_reg != kNoRegister); 812 ASSERT(temp_reg != kNoRegister);
812 ASSERT(temp_reg != TMP); 813 ASSERT(temp_reg != TMP);
813 ASSERT(cid > 0); 814 ASSERT(cid > 0);
814 Isolate* isolate = Isolate::Current(); 815 intptr_t counter_offset =
815 ClassTable* class_table = isolate->class_table(); 816 ClassTable::CounterOffsetFor(cid, space == Heap::kNew);
816 if (cid < kNumPredefinedCids) { 817 if (inline_isolate) {
817 const uword class_heap_stats_table_address = 818 ClassTable* class_table = Isolate::Current()->class_table();
818 class_table->PredefinedClassHeapStatsTableAddress(); 819 ClassHeapStats** table_ptr = class_table->TableAddressFor(cid);
819 const uword class_offset = cid * sizeof(ClassHeapStats); // NOLINT 820 if (cid < kNumPredefinedCids) {
820 const uword count_field_offset = (space == Heap::kNew) ? 821 LoadImmediate(
821 ClassHeapStats::allocated_since_gc_new_space_offset() : 822 temp_reg, reinterpret_cast<uword>(*table_ptr) + counter_offset);
822 ClassHeapStats::allocated_since_gc_old_space_offset(); 823 } else {
823 LoadImmediate(temp_reg, class_heap_stats_table_address + class_offset); 824 ASSERT(temp_reg != kNoRegister);
824 const Address& count_address = Address(temp_reg, count_field_offset); 825 LoadImmediate(temp_reg, reinterpret_cast<uword>(table_ptr));
825 lw(TMP, count_address); 826 lw(temp_reg, Address(temp_reg, 0));
826 AddImmediate(TMP, 1); 827 AddImmediate(temp_reg, counter_offset);
827 sw(TMP, count_address); 828 }
828 } else { 829 } else {
829 ASSERT(temp_reg != kNoRegister); 830 LoadIsolate(temp_reg);
830 const uword class_offset = cid * sizeof(ClassHeapStats); // NOLINT 831 intptr_t table_offset =
831 const uword count_field_offset = (space == Heap::kNew) ? 832 Isolate::class_table_offset() + ClassTable::TableOffsetFor(cid);
832 ClassHeapStats::allocated_since_gc_new_space_offset() : 833 lw(temp_reg, Address(temp_reg, table_offset));
833 ClassHeapStats::allocated_since_gc_old_space_offset(); 834 AddImmediate(temp_reg, counter_offset);
834 LoadImmediate(temp_reg, class_table->ClassStatsTableAddress());
835 lw(temp_reg, Address(temp_reg, 0));
836 AddImmediate(temp_reg, class_offset);
837 lw(TMP, Address(temp_reg, count_field_offset));
838 AddImmediate(TMP, 1);
839 sw(TMP, Address(temp_reg, count_field_offset));
840 } 835 }
836 lw(TMP, Address(temp_reg, 0));
837 AddImmediate(TMP, 1);
838 sw(TMP, Address(temp_reg, 0));
841 } 839 }
842 840
843 841
844 void Assembler::UpdateAllocationStatsWithSize(intptr_t cid, 842 void Assembler::UpdateAllocationStatsWithSize(intptr_t cid,
845 Register size_reg, 843 Register size_reg,
846 Register temp_reg, 844 Register temp_reg,
847 Heap::Space space) { 845 Heap::Space space,
846 bool inline_isolate) {
848 ASSERT(!in_delay_slot_); 847 ASSERT(!in_delay_slot_);
849 ASSERT(temp_reg != kNoRegister); 848 ASSERT(temp_reg != kNoRegister);
850 ASSERT(cid > 0); 849 ASSERT(cid > 0);
851 ASSERT(temp_reg != TMP); 850 ASSERT(temp_reg != TMP);
852 Isolate* isolate = Isolate::Current(); 851 const uword class_offset = ClassTable::ClassOffsetFor(cid);
853 ClassTable* class_table = isolate->class_table(); 852 const uword count_field_offset = (space == Heap::kNew) ?
854 if (cid < kNumPredefinedCids) { 853 ClassHeapStats::allocated_since_gc_new_space_offset() :
855 const uword class_heap_stats_table_address = 854 ClassHeapStats::allocated_since_gc_old_space_offset();
856 class_table->PredefinedClassHeapStatsTableAddress(); 855 const uword size_field_offset = (space == Heap::kNew) ?
857 const uword class_offset = cid * sizeof(ClassHeapStats); // NOLINT 856 ClassHeapStats::allocated_size_since_gc_new_space_offset() :
858 const uword count_field_offset = (space == Heap::kNew) ? 857 ClassHeapStats::allocated_size_since_gc_old_space_offset();
859 ClassHeapStats::allocated_since_gc_new_space_offset() : 858 if (inline_isolate) {
860 ClassHeapStats::allocated_since_gc_old_space_offset(); 859 ClassTable* class_table = Isolate::Current()->class_table();
861 const uword size_field_offset = (space == Heap::kNew) ? 860 ClassHeapStats** table_ptr = class_table->TableAddressFor(cid);
862 ClassHeapStats::allocated_size_since_gc_new_space_offset() : 861 if (cid < kNumPredefinedCids) {
863 ClassHeapStats::allocated_size_since_gc_old_space_offset(); 862 LoadImmediate(temp_reg,
864 LoadImmediate(temp_reg, class_heap_stats_table_address + class_offset); 863 reinterpret_cast<uword>(*table_ptr) + class_offset);
865 const Address& count_address = Address(temp_reg, count_field_offset); 864 } else {
866 const Address& size_address = Address(temp_reg, size_field_offset); 865 ASSERT(temp_reg != kNoRegister);
867 lw(TMP, count_address); 866 LoadImmediate(temp_reg, reinterpret_cast<uword>(table_ptr));
868 AddImmediate(TMP, 1); 867 lw(temp_reg, Address(temp_reg, 0));
869 sw(TMP, count_address); 868 AddImmediate(temp_reg, class_offset);
870 lw(TMP, size_address); 869 }
871 addu(TMP, TMP, size_reg);
872 sw(TMP, size_address);
873 } else { 870 } else {
874 ASSERT(temp_reg != kNoRegister); 871 LoadIsolate(temp_reg);
875 const uword class_offset = cid * sizeof(ClassHeapStats); // NOLINT 872 intptr_t table_offset =
876 const uword count_field_offset = (space == Heap::kNew) ? 873 Isolate::class_table_offset() + ClassTable::TableOffsetFor(cid);
877 ClassHeapStats::allocated_since_gc_new_space_offset() : 874 lw(temp_reg, Address(temp_reg, table_offset));
878 ClassHeapStats::allocated_since_gc_old_space_offset();
879 const uword size_field_offset = (space == Heap::kNew) ?
880 ClassHeapStats::allocated_size_since_gc_new_space_offset() :
881 ClassHeapStats::allocated_size_since_gc_old_space_offset();
882 LoadImmediate(temp_reg, class_table->ClassStatsTableAddress());
883 lw(temp_reg, Address(temp_reg, 0));
884 AddImmediate(temp_reg, class_offset); 875 AddImmediate(temp_reg, class_offset);
885 lw(TMP, Address(temp_reg, count_field_offset));
886 AddImmediate(TMP, 1);
887 sw(TMP, Address(temp_reg, count_field_offset));
888 lw(TMP, Address(temp_reg, size_field_offset));
889 addu(TMP, TMP, size_reg);
890 sw(TMP, Address(temp_reg, size_field_offset));
891 } 876 }
877 lw(TMP, Address(temp_reg, count_field_offset));
878 AddImmediate(TMP, 1);
879 sw(TMP, Address(temp_reg, count_field_offset));
880 lw(TMP, Address(temp_reg, size_field_offset));
881 addu(TMP, TMP, size_reg);
882 sw(TMP, Address(temp_reg, size_field_offset));
892 } 883 }
893 884
894 885
895 void Assembler::MaybeTraceAllocation(intptr_t cid, 886 void Assembler::MaybeTraceAllocation(intptr_t cid,
896 Register temp_reg, 887 Register temp_reg,
897 Label* trace) { 888 Label* trace) {
898 ASSERT(cid > 0); 889 ASSERT(cid > 0);
899 ASSERT(!in_delay_slot_); 890 ASSERT(!in_delay_slot_);
900 ASSERT(temp_reg != kNoRegister); 891 ASSERT(temp_reg != kNoRegister);
901 ASSERT(temp_reg != TMP); 892 ASSERT(temp_reg != TMP);
902 Isolate* isolate = Isolate::Current(); 893 intptr_t state_offset;
903 ClassTable* class_table = isolate->class_table(); 894 ClassTable* class_table = Isolate::Current()->class_table();
904 const uword class_offset = cid * sizeof(ClassHeapStats); // NOLINT 895 ClassHeapStats** table_ptr =
896 class_table->StateAddressFor(cid, &state_offset);
905 if (cid < kNumPredefinedCids) { 897 if (cid < kNumPredefinedCids) {
906 const uword class_heap_stats_table_address = 898 LoadImmediate(temp_reg, reinterpret_cast<uword>(*table_ptr) + state_offset);
907 class_table->PredefinedClassHeapStatsTableAddress();
908 LoadImmediate(temp_reg, class_heap_stats_table_address + class_offset);
909 } else { 899 } else {
910 LoadImmediate(temp_reg, class_table->ClassStatsTableAddress()); 900 LoadImmediate(temp_reg, reinterpret_cast<uword>(table_ptr));
911 lw(temp_reg, Address(temp_reg, 0)); 901 lw(temp_reg, Address(temp_reg, 0));
912 AddImmediate(temp_reg, class_offset); 902 AddImmediate(temp_reg, state_offset);
913 } 903 }
914 const uword state_offset = ClassHeapStats::state_offset(); 904 lw(temp_reg, Address(temp_reg, 0));
915 const Address& state_address = Address(temp_reg, state_offset);
916 lw(temp_reg, state_address);
917 andi(CMPRES1, temp_reg, Immediate(ClassHeapStats::TraceAllocationMask())); 905 andi(CMPRES1, temp_reg, Immediate(ClassHeapStats::TraceAllocationMask()));
918 bne(CMPRES1, ZR, trace); 906 bne(CMPRES1, ZR, trace);
919 } 907 }
920 908
921 909
922 void Assembler::TryAllocate(const Class& cls, 910 void Assembler::TryAllocate(const Class& cls,
923 Label* failure, 911 Label* failure,
924 Register instance_reg, 912 Register instance_reg,
925 Register temp_reg) { 913 Register temp_reg) {
926 ASSERT(!in_delay_slot_); 914 ASSERT(!in_delay_slot_);
(...skipping 352 matching lines...) Expand 10 before | Expand all | Expand 10 after
1279 Label stop; 1267 Label stop;
1280 b(&stop); 1268 b(&stop);
1281 Emit(reinterpret_cast<int32_t>(message)); 1269 Emit(reinterpret_cast<int32_t>(message));
1282 Bind(&stop); 1270 Bind(&stop);
1283 break_(Instr::kStopMessageCode); 1271 break_(Instr::kStopMessageCode);
1284 } 1272 }
1285 1273
1286 } // namespace dart 1274 } // namespace dart
1287 1275
1288 #endif // defined TARGET_ARCH_MIPS 1276 #endif // defined TARGET_ARCH_MIPS
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