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Side by Side Diff: runtime/vm/assembler_mips.cc

Issue 1241863002: VM: Refactor allocation stats code and remove duplicate code. (Closed) Base URL: git@github.com:dart-lang/sdk.git@master
Patch Set: make context allocation isolate-independent Created 5 years, 5 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/globals.h" // NOLINT 5 #include "vm/globals.h" // NOLINT
6 #if defined(TARGET_ARCH_MIPS) 6 #if defined(TARGET_ARCH_MIPS)
7 7
8 #include "vm/assembler.h" 8 #include "vm/assembler.h"
9 #include "vm/longjump.h" 9 #include "vm/longjump.h"
10 #include "vm/runtime_entry.h" 10 #include "vm/runtime_entry.h"
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799 lw(RA, Address(SP, 2 * kWordSize)); 799 lw(RA, Address(SP, 2 * kWordSize));
800 lw(FP, Address(SP, 1 * kWordSize)); 800 lw(FP, Address(SP, 1 * kWordSize));
801 lw(PP, Address(SP, 0 * kWordSize)); 801 lw(PP, Address(SP, 0 * kWordSize));
802 jr(ra); 802 jr(ra);
803 delay_slot()->addiu(SP, SP, Immediate(4 * kWordSize)); 803 delay_slot()->addiu(SP, SP, Immediate(4 * kWordSize));
804 } 804 }
805 805
806 806
807 void Assembler::UpdateAllocationStats(intptr_t cid, 807 void Assembler::UpdateAllocationStats(intptr_t cid,
808 Register temp_reg, 808 Register temp_reg,
809 Heap::Space space) { 809 Heap::Space space,
810 bool inline_isolate) {
810 ASSERT(!in_delay_slot_); 811 ASSERT(!in_delay_slot_);
811 ASSERT(temp_reg != kNoRegister); 812 ASSERT(temp_reg != kNoRegister);
812 ASSERT(temp_reg != TMP); 813 ASSERT(temp_reg != TMP);
813 ASSERT(cid > 0); 814 ASSERT(cid > 0);
814 Isolate* isolate = Isolate::Current(); 815 intptr_t counter_offset;
815 ClassTable* class_table = isolate->class_table(); 816 ClassTable* class_table = Isolate::Current()->class_table();
816 if (cid < kNumPredefinedCids) { 817 ClassHeapStats** table_ptr = class_table->CountAddressFor(
817 const uword class_heap_stats_table_address = 818 cid, space == Heap::kNew, &counter_offset);
818 class_table->PredefinedClassHeapStatsTableAddress(); 819 if (cid < kNumPredefinedCids && inline_isolate) {
819 const uword class_offset = cid * sizeof(ClassHeapStats); // NOLINT 820 LoadImmediate(
820 const uword count_field_offset = (space == Heap::kNew) ? 821 temp_reg, reinterpret_cast<uword>(*table_ptr) + counter_offset);
821 ClassHeapStats::allocated_since_gc_new_space_offset() : 822 lw(TMP, Address(temp_reg, 0));
822 ClassHeapStats::allocated_since_gc_old_space_offset();
823 LoadImmediate(temp_reg, class_heap_stats_table_address + class_offset);
824 const Address& count_address = Address(temp_reg, count_field_offset);
825 lw(TMP, count_address);
826 AddImmediate(TMP, 1); 823 AddImmediate(TMP, 1);
827 sw(TMP, count_address); 824 sw(TMP, Address(temp_reg, 0));
828 } else { 825 } else {
829 ASSERT(temp_reg != kNoRegister); 826 ASSERT(temp_reg != kNoRegister);
830 const uword class_offset = cid * sizeof(ClassHeapStats); // NOLINT 827 if (inline_isolate) {
831 const uword count_field_offset = (space == Heap::kNew) ? 828 LoadImmediate(temp_reg, reinterpret_cast<uword>(table_ptr));
832 ClassHeapStats::allocated_since_gc_new_space_offset() : 829 lw(temp_reg, Address(temp_reg, 0));
833 ClassHeapStats::allocated_since_gc_old_space_offset(); 830 } else {
834 LoadImmediate(temp_reg, class_table->ClassStatsTableAddress()); 831 LoadIsolate(temp_reg);
835 lw(temp_reg, Address(temp_reg, 0)); 832 intptr_t table_offset =
836 AddImmediate(temp_reg, class_offset); 833 Isolate::class_table_offset() + ClassTable::TableOffsetFor(cid);
837 lw(TMP, Address(temp_reg, count_field_offset)); 834 lw(temp_reg, Address(temp_reg, table_offset));
835 }
836 AddImmediate(temp_reg, counter_offset);
837 lw(TMP, Address(temp_reg, 0));
838 AddImmediate(TMP, 1); 838 AddImmediate(TMP, 1);
839 sw(TMP, Address(temp_reg, count_field_offset)); 839 sw(TMP, Address(temp_reg, 0));
840 } 840 }
841 } 841 }
842 842
843 843
844 void Assembler::UpdateAllocationStatsWithSize(intptr_t cid, 844 void Assembler::UpdateAllocationStatsWithSize(intptr_t cid,
845 Register size_reg, 845 Register size_reg,
846 Register temp_reg, 846 Register temp_reg,
847 Heap::Space space) { 847 Heap::Space space,
848 bool inline_isolate) {
848 ASSERT(!in_delay_slot_); 849 ASSERT(!in_delay_slot_);
849 ASSERT(temp_reg != kNoRegister); 850 ASSERT(temp_reg != kNoRegister);
850 ASSERT(cid > 0); 851 ASSERT(cid > 0);
851 ASSERT(temp_reg != TMP); 852 ASSERT(temp_reg != TMP);
852 Isolate* isolate = Isolate::Current(); 853 ClassTable* class_table = Isolate::Current()->class_table();
853 ClassTable* class_table = isolate->class_table(); 854 ClassHeapStats** table_ptr = class_table->TableAddressFor(cid);
854 if (cid < kNumPredefinedCids) { 855 const uword class_offset = ClassTable::ClassOffsetFor(cid);
855 const uword class_heap_stats_table_address = 856 const uword count_field_offset = (space == Heap::kNew) ?
856 class_table->PredefinedClassHeapStatsTableAddress(); 857 ClassHeapStats::allocated_since_gc_new_space_offset() :
857 const uword class_offset = cid * sizeof(ClassHeapStats); // NOLINT 858 ClassHeapStats::allocated_since_gc_old_space_offset();
858 const uword count_field_offset = (space == Heap::kNew) ? 859 const uword size_field_offset = (space == Heap::kNew) ?
859 ClassHeapStats::allocated_since_gc_new_space_offset() : 860 ClassHeapStats::allocated_size_since_gc_new_space_offset() :
860 ClassHeapStats::allocated_since_gc_old_space_offset(); 861 ClassHeapStats::allocated_size_since_gc_old_space_offset();
861 const uword size_field_offset = (space == Heap::kNew) ? 862 if (cid < kNumPredefinedCids && inline_isolate) {
862 ClassHeapStats::allocated_size_since_gc_new_space_offset() : 863 LoadImmediate(temp_reg, reinterpret_cast<uword>(*table_ptr) + class_offset);
863 ClassHeapStats::allocated_size_since_gc_old_space_offset();
864 LoadImmediate(temp_reg, class_heap_stats_table_address + class_offset);
865 const Address& count_address = Address(temp_reg, count_field_offset); 864 const Address& count_address = Address(temp_reg, count_field_offset);
866 const Address& size_address = Address(temp_reg, size_field_offset); 865 const Address& size_address = Address(temp_reg, size_field_offset);
867 lw(TMP, count_address); 866 lw(TMP, count_address);
868 AddImmediate(TMP, 1); 867 AddImmediate(TMP, 1);
869 sw(TMP, count_address); 868 sw(TMP, count_address);
870 lw(TMP, size_address); 869 lw(TMP, size_address);
871 addu(TMP, TMP, size_reg); 870 addu(TMP, TMP, size_reg);
872 sw(TMP, size_address); 871 sw(TMP, size_address);
873 } else { 872 } else {
874 ASSERT(temp_reg != kNoRegister); 873 ASSERT(temp_reg != kNoRegister);
875 const uword class_offset = cid * sizeof(ClassHeapStats); // NOLINT 874 if (inline_isolate) {
876 const uword count_field_offset = (space == Heap::kNew) ? 875 LoadImmediate(temp_reg, reinterpret_cast<uword>(table_ptr));
877 ClassHeapStats::allocated_since_gc_new_space_offset() : 876 lw(temp_reg, Address(temp_reg, 0));
878 ClassHeapStats::allocated_since_gc_old_space_offset(); 877 } else {
879 const uword size_field_offset = (space == Heap::kNew) ? 878 LoadIsolate(temp_reg);
880 ClassHeapStats::allocated_size_since_gc_new_space_offset() : 879 intptr_t table_offset =
881 ClassHeapStats::allocated_size_since_gc_old_space_offset(); 880 Isolate::class_table_offset() + ClassTable::TableOffsetFor(cid);
882 LoadImmediate(temp_reg, class_table->ClassStatsTableAddress()); 881 lw(temp_reg, Address(temp_reg, table_offset));
883 lw(temp_reg, Address(temp_reg, 0)); 882 }
884 AddImmediate(temp_reg, class_offset); 883 AddImmediate(temp_reg, class_offset);
885 lw(TMP, Address(temp_reg, count_field_offset)); 884 lw(TMP, Address(temp_reg, count_field_offset));
886 AddImmediate(TMP, 1); 885 AddImmediate(TMP, 1);
887 sw(TMP, Address(temp_reg, count_field_offset)); 886 sw(TMP, Address(temp_reg, count_field_offset));
888 lw(TMP, Address(temp_reg, size_field_offset)); 887 lw(TMP, Address(temp_reg, size_field_offset));
889 addu(TMP, TMP, size_reg); 888 addu(TMP, TMP, size_reg);
890 sw(TMP, Address(temp_reg, size_field_offset)); 889 sw(TMP, Address(temp_reg, size_field_offset));
891 } 890 }
892 } 891 }
893 892
894 893
895 void Assembler::MaybeTraceAllocation(intptr_t cid, 894 void Assembler::MaybeTraceAllocation(intptr_t cid,
896 Register temp_reg, 895 Register temp_reg,
897 Label* trace) { 896 Label* trace) {
898 ASSERT(cid > 0); 897 ASSERT(cid > 0);
899 ASSERT(!in_delay_slot_); 898 ASSERT(!in_delay_slot_);
900 ASSERT(temp_reg != kNoRegister); 899 ASSERT(temp_reg != kNoRegister);
901 ASSERT(temp_reg != TMP); 900 ASSERT(temp_reg != TMP);
902 Isolate* isolate = Isolate::Current(); 901 intptr_t state_offset;
903 ClassTable* class_table = isolate->class_table(); 902 ClassTable* class_table = Isolate::Current()->class_table();
904 const uword class_offset = cid * sizeof(ClassHeapStats); // NOLINT 903 ClassHeapStats** table_ptr =
904 class_table->StateAddressFor(cid, &state_offset);
905 if (cid < kNumPredefinedCids) { 905 if (cid < kNumPredefinedCids) {
906 const uword class_heap_stats_table_address = 906 LoadImmediate(temp_reg, reinterpret_cast<uword>(*table_ptr) + state_offset);
907 class_table->PredefinedClassHeapStatsTableAddress();
908 LoadImmediate(temp_reg, class_heap_stats_table_address + class_offset);
909 } else { 907 } else {
910 LoadImmediate(temp_reg, class_table->ClassStatsTableAddress()); 908 LoadImmediate(temp_reg, reinterpret_cast<uword>(table_ptr));
911 lw(temp_reg, Address(temp_reg, 0)); 909 lw(temp_reg, Address(temp_reg, 0));
912 AddImmediate(temp_reg, class_offset); 910 AddImmediate(temp_reg, state_offset);
913 } 911 }
914 const uword state_offset = ClassHeapStats::state_offset(); 912 lw(temp_reg, Address(temp_reg, 0));
915 const Address& state_address = Address(temp_reg, state_offset);
916 lw(temp_reg, state_address);
917 andi(CMPRES1, temp_reg, Immediate(ClassHeapStats::TraceAllocationMask())); 913 andi(CMPRES1, temp_reg, Immediate(ClassHeapStats::TraceAllocationMask()));
918 bne(CMPRES1, ZR, trace); 914 bne(CMPRES1, ZR, trace);
919 } 915 }
920 916
921 917
922 void Assembler::TryAllocate(const Class& cls, 918 void Assembler::TryAllocate(const Class& cls,
923 Label* failure, 919 Label* failure,
924 Register instance_reg, 920 Register instance_reg,
925 Register temp_reg) { 921 Register temp_reg) {
926 ASSERT(!in_delay_slot_); 922 ASSERT(!in_delay_slot_);
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1279 Label stop; 1275 Label stop;
1280 b(&stop); 1276 b(&stop);
1281 Emit(reinterpret_cast<int32_t>(message)); 1277 Emit(reinterpret_cast<int32_t>(message));
1282 Bind(&stop); 1278 Bind(&stop);
1283 break_(Instr::kStopMessageCode); 1279 break_(Instr::kStopMessageCode);
1284 } 1280 }
1285 1281
1286 } // namespace dart 1282 } // namespace dart
1287 1283
1288 #endif // defined TARGET_ARCH_MIPS 1284 #endif // defined TARGET_ARCH_MIPS
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