| Index: src/arm/assembler-arm.cc
|
| ===================================================================
|
| --- src/arm/assembler-arm.cc (revision 13713)
|
| +++ src/arm/assembler-arm.cc (working copy)
|
| @@ -1495,6 +1495,31 @@
|
| }
|
|
|
|
|
| +// Preload data instruction
|
| +void Assembler::pld(const MemOperand& src) {
|
| + Instr instr = kCondMask | B26 | B | L | kRdMask;
|
| + int am = src.am_;
|
| + ASSERT((am & (P | W)) == P);
|
| + if (!src.rm_.is_valid()) {
|
| + // Immediate offset.
|
| + int offset_12 = src.offset_;
|
| + if (offset_12 < 0) {
|
| + offset_12 = -offset_12;
|
| + am ^= U;
|
| + }
|
| + ASSERT(offset_12 >= 0); // no masking needed
|
| + instr |= offset_12;
|
| + } else {
|
| + // Register offset (shift_imm_ and shift_op_ are 0) or scaled
|
| + // register offset the constructors make sure than both shift_imm_
|
| + // and shift_op_ are initialized.
|
| + ASSERT(!src.rm_.is(pc));
|
| + instr |= B25 | src.shift_imm_*B7 | src.shift_op_ | src.rm_.code();
|
| + }
|
| + emit(instr | am | src.rn_.code()*B16);
|
| +}
|
| +
|
| +
|
| // Load/Store instructions.
|
| void Assembler::ldr(Register dst, const MemOperand& src, Condition cond) {
|
| if (dst.is(pc)) {
|
|
|