ARM: Fix disassembly of some VFP instructions with condition codes

test/cctest/test-disasm-arm.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 414 matching lines @@
 
   if (CpuFeatures::IsSupported(VFP3)) {
     CpuFeatures::Scope scope(VFP3);
     COMPARE(vmov(d0, r2, r3),
             "ec432b10       vmov d0, r2, r3");
     COMPARE(vmov(r2, r3, d0),
             "ec532b10       vmov r2, r3, d0");
     COMPARE(vmov(d0, d1),
             "eeb00b41       vmov.f64 d0, d1");
     COMPARE(vmov(d3, d3, eq),
-            "0eb03b43       vmov.f64eq d3, d3");
+            "0eb03b43       vmoveq.f64 d3, d3");
 
     COMPARE(vmov(s0, s31),
             "eeb00a6f       vmov.f32 s0, s31");
     COMPARE(vmov(s31, s0),
             "eef0fa40       vmov.f32 s31, s0");
     COMPARE(vmov(r0, s0),
             "ee100a10       vmov r0, s0");
     COMPARE(vmov(r10, s31),
             "ee1faa90       vmov r10, s31");
     COMPARE(vmov(s0, r0),
             "ee000a10       vmov s0, r0");
     COMPARE(vmov(s31, r10),
             "ee0faa90       vmov s31, r10");
 
     COMPARE(vabs(d0, d1),
             "eeb00bc1       vabs.f64 d0, d1");
     COMPARE(vabs(d3, d4, mi),
-            "4eb03bc4       vabs.f64mi d3, d4");
+            "4eb03bc4       vabsmi.f64 d3, d4");
 
     COMPARE(vneg(d0, d1),
             "eeb10b41       vneg.f64 d0, d1");
     COMPARE(vneg(d3, d4, mi),
-            "4eb13b44       vneg.f64mi d3, d4");
+            "4eb13b44       vnegmi.f64 d3, d4");
 
     COMPARE(vadd(d0, d1, d2),
             "ee310b02       vadd.f64 d0, d1, d2");
     COMPARE(vadd(d3, d4, d5, mi),
-            "4e343b05       vadd.f64mi d3, d4, d5");
+            "4e343b05       vaddmi.f64 d3, d4, d5");
 
     COMPARE(vsub(d0, d1, d2),
             "ee310b42       vsub.f64 d0, d1, d2");
     COMPARE(vsub(d3, d4, d5, ne),
-            "1e343b45       vsub.f64ne d3, d4, d5");
+            "1e343b45       vsubne.f64 d3, d4, d5");
 
     COMPARE(vmul(d2, d1, d0),
             "ee212b00       vmul.f64 d2, d1, d0");
     COMPARE(vmul(d6, d4, d5, cc),
-            "3e246b05       vmul.f64cc d6, d4, d5");
+            "3e246b05       vmulcc.f64 d6, d4, d5");
 
     COMPARE(vdiv(d2, d2, d2),
             "ee822b02       vdiv.f64 d2, d2, d2");
     COMPARE(vdiv(d6, d7, d7, hi),
-            "8e876b07       vdiv.f64hi d6, d7, d7");
+            "8e876b07       vdivhi.f64 d6, d7, d7");
 
     COMPARE(vcmp(d0, d1),
             "eeb40b41       vcmp.f64 d0, d1");
     COMPARE(vcmp(d0, 0.0),
             "eeb50b40       vcmp.f64 d0, #0.0");
 
     COMPARE(vsqrt(d0, d0),
             "eeb10bc0       vsqrt.f64 d0, d0");
     COMPARE(vsqrt(d2, d3, ne),
-            "1eb12bc3       vsqrt.f64ne d2, d3");
+            "1eb12bc3       vsqrtne.f64 d2, d3");
 
     COMPARE(vmov(d0, 1.0),
             "eeb70b00       vmov.f64 d0, #1");
     COMPARE(vmov(d2, -13.0),
             "eeba2b0a       vmov.f64 d2, #-13");
 
     COMPARE(vmov(d0, VmovIndexLo, r0),
             "ee000b10       vmov.32 d0[0], r0");
     COMPARE(vmov(d0, VmovIndexHi, r0),
             "ee200b10       vmov.32 d0[1], r0");
@@ skipping 59 matching lines @@
     COMPARE(vldm(ia, r5, s2, s5),
             "ec951a04       vldmia r5, {s2-s5}");
     COMPARE(vstm(ia, r6, s0, s31),
             "ec860a20       vstmia r6, {s0-s31}");
     COMPARE(vldm(ia, r7, s0, s31),
             "ec970a20       vldmia r7, {s0-s31}");
 
     COMPARE(vmla(d2, d1, d0),
             "ee012b00       vmla.f64 d2, d1, d0");
     COMPARE(vmla(d6, d4, d5, cc),
-            "3e046b05       vmla.f64cc d6, d4, d5");
+            "3e046b05       vmlacc.f64 d6, d4, d5");
 
     COMPARE(vmls(d2, d1, d0),
             "ee012b40       vmls.f64 d2, d1, d0");
     COMPARE(vmls(d6, d4, d5, cc),
-            "3e046b45       vmls.f64cc d6, d4, d5");
+            "3e046b45       vmlscc.f64 d6, d4, d5");
 
     COMPARE(vcvt_u32_f64(s0, d0),
             "eebc0bc0       vcvt.u32.f64 s0, d0");
     COMPARE(vcvt_s32_f64(s0, d0),
             "eebd0bc0       vcvt.s32.f64 s0, d0");
     COMPARE(vcvt_f64_u32(d0, s1),
             "eeb80b60       vcvt.f64.u32 d0, s1");
     COMPARE(vcvt_f64_s32(d0, s1),
             "eeb80be0       vcvt.f64.s32 d0, s1");
     COMPARE(vcvt_f32_s32(s0, s2),
@@ skipping 277 matching lines @@
     COMPARE(strd(r8, r9, MemOperand(r9, -127, PostIndex)),
             "e04987ff       strd r8, [r9], #-127");
     COMPARE(strd(r10, fp, MemOperand(fp, 127, PreIndex)),
             "e1eba7ff       strd r10, [fp, #+127]!");
     COMPARE(strd(ip, sp, MemOperand(sp, -127, PreIndex)),
             "e16dc7ff       strd ip, [sp, #-127]!");
   }
 
   VERIFY_RUN();
 }