| Index: src/arm/assembler-arm.cc
|
| diff --git a/src/arm/assembler-arm.cc b/src/arm/assembler-arm.cc
|
| index 7cd0a1753eff2b9f663a44b35b05bfb9f4b1e2c7..a8c32d98bcf4a4f6e648da6e09165dadeb89e698 100644
|
| --- a/src/arm/assembler-arm.cc
|
| +++ b/src/arm/assembler-arm.cc
|
| @@ -2536,6 +2536,24 @@ void Assembler::vmla(const DwVfpRegister dst,
|
| }
|
|
|
|
|
| +void Assembler::vmls(const DwVfpRegister dst,
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| + const DwVfpRegister src1,
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| + const DwVfpRegister src2,
|
| + const Condition cond) {
|
| + // Instruction details available in ARM DDI 0406C.b, A8-932.
|
| + // cond(31-28) | 11100(27-23) | D(22) | 00(21-20) | Vn(19-16) |
|
| + // Vd(15-12) | 101(11-9) | sz=1(8) | N(7) | op=1(6) | M(5) | 0(4) | Vm(3-0)
|
| + int vd, d;
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| + dst.split_code(&vd, &d);
|
| + int vn, n;
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| + src1.split_code(&vn, &n);
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| + int vm, m;
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| + src2.split_code(&vm, &m);
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| + emit(cond | 0x1C*B23 | d*B22 | vn*B16 | vd*B12 | 0x5*B9 | B8 | n*B7 | B6 |
|
| + m*B5 | vm);
|
| +}
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| +
|
| +
|
| void Assembler::vdiv(const DwVfpRegister dst,
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| const DwVfpRegister src1,
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| const DwVfpRegister src2,
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|
|