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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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2114 | 2114 |
2115 // Move the high part of the double into the higher of the | 2115 // Move the high part of the double into the higher of the |
2116 // corresponsing S registers of D register dst. | 2116 // corresponsing S registers of D register dst. |
2117 mov(ip, Operand(hi)); | 2117 mov(ip, Operand(hi)); |
2118 vmov(dst.high(), ip, cond); | 2118 vmov(dst.high(), ip, cond); |
2119 } else { | 2119 } else { |
2120 // D16-D31 does not have S registers, so move the low and high parts | 2120 // D16-D31 does not have S registers, so move the low and high parts |
2121 // directly to the D register using vmov.32. | 2121 // directly to the D register using vmov.32. |
2122 // Note: This may be slower, so we only do this when we have to. | 2122 // Note: This may be slower, so we only do this when we have to. |
2123 mov(ip, Operand(lo)); | 2123 mov(ip, Operand(lo)); |
2124 vmov(dst, 0, ip, cond); | 2124 vmov(dst, VmovIndexLo, ip, cond); |
2125 mov(ip, Operand(hi)); | 2125 mov(ip, Operand(hi)); |
2126 vmov(dst, 1, ip, cond); | 2126 vmov(dst, VmovIndexHi, ip, cond); |
2127 } | 2127 } |
2128 } else { | 2128 } else { |
2129 // Move the low and high parts of the double to a D register in one | 2129 // Move the low and high parts of the double to a D register in one |
2130 // instruction. | 2130 // instruction. |
2131 mov(ip, Operand(lo)); | 2131 mov(ip, Operand(lo)); |
2132 mov(scratch, Operand(hi)); | 2132 mov(scratch, Operand(hi)); |
2133 vmov(dst, ip, scratch, cond); | 2133 vmov(dst, ip, scratch, cond); |
2134 } | 2134 } |
2135 } | 2135 } |
2136 } | 2136 } |
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2160 int vd, d; | 2160 int vd, d; |
2161 dst.split_code(&vd, &d); | 2161 dst.split_code(&vd, &d); |
2162 int vm, m; | 2162 int vm, m; |
2163 src.split_code(&vm, &m); | 2163 src.split_code(&vm, &m); |
2164 emit(cond | 0x1D*B23 | d*B22 | 0x3*B20 | vd*B12 | 0x5*B9 | B8 | B6 | m*B5 | | 2164 emit(cond | 0x1D*B23 | d*B22 | 0x3*B20 | vd*B12 | 0x5*B9 | B8 | B6 | m*B5 | |
2165 vm); | 2165 vm); |
2166 } | 2166 } |
2167 | 2167 |
2168 | 2168 |
2169 void Assembler::vmov(const DwVfpRegister dst, | 2169 void Assembler::vmov(const DwVfpRegister dst, |
2170 int index, | 2170 const VmovIndex index, |
2171 const Register src, | 2171 const Register src, |
2172 const Condition cond) { | 2172 const Condition cond) { |
2173 // Dd[index] = Rt | 2173 // Dd[index] = Rt |
2174 // Instruction details available in ARM DDI 0406C.b, A8-940. | 2174 // Instruction details available in ARM DDI 0406C.b, A8-940. |
2175 // cond(31-28) | 1110(27-24) | 0(23) | opc1=0index(22-21) | 0(20) | | 2175 // cond(31-28) | 1110(27-24) | 0(23) | opc1=0index(22-21) | 0(20) | |
2176 // Vd(19-16) | Rt(15-12) | 1011(11-8) | D(7) | opc2=00(6-5) | 1(4) | 0000(3-0) | 2176 // Vd(19-16) | Rt(15-12) | 1011(11-8) | D(7) | opc2=00(6-5) | 1(4) | 0000(3-0) |
2177 ASSERT(CpuFeatures::IsEnabled(VFP2)); | 2177 ASSERT(CpuFeatures::IsEnabled(VFP2)); |
2178 ASSERT(index == 0 || index == 1); | 2178 ASSERT(index.index == 0 || index.index == 1); |
2179 int vd, d; | 2179 int vd, d; |
2180 dst.split_code(&vd, &d); | 2180 dst.split_code(&vd, &d); |
2181 emit(cond | 0xE*B24 | index*B21 | vd*B16 | src.code()*B12 | 0xB*B8 | d*B7 | | 2181 emit(cond | 0xE*B24 | index.index*B21 | vd*B16 | src.code()*B12 | 0xB*B8 | |
2182 B4); | 2182 d*B7 | B4); |
2183 } | 2183 } |
2184 | 2184 |
2185 | 2185 |
2186 void Assembler::vmov(const DwVfpRegister dst, | 2186 void Assembler::vmov(const DwVfpRegister dst, |
2187 const Register src1, | 2187 const Register src1, |
2188 const Register src2, | 2188 const Register src2, |
2189 const Condition cond) { | 2189 const Condition cond) { |
2190 // Dm = <Rt,Rt2>. | 2190 // Dm = <Rt,Rt2>. |
2191 // Instruction details available in ARM DDI 0406C.b, A8-948. | 2191 // Instruction details available in ARM DDI 0406C.b, A8-948. |
2192 // cond(31-28) | 1100(27-24)| 010(23-21) | op=0(20) | Rt2(19-16) | | 2192 // cond(31-28) | 1100(27-24)| 010(23-21) | op=0(20) | Rt2(19-16) | |
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3026 | 3026 |
3027 // Since a constant pool was just emitted, move the check offset forward by | 3027 // Since a constant pool was just emitted, move the check offset forward by |
3028 // the standard interval. | 3028 // the standard interval. |
3029 next_buffer_check_ = pc_offset() + kCheckPoolInterval; | 3029 next_buffer_check_ = pc_offset() + kCheckPoolInterval; |
3030 } | 3030 } |
3031 | 3031 |
3032 | 3032 |
3033 } } // namespace v8::internal | 3033 } } // namespace v8::internal |
3034 | 3034 |
3035 #endif // V8_TARGET_ARCH_ARM | 3035 #endif // V8_TARGET_ARCH_ARM |
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