src/trusted/validator_arm/gen/arm32_decode_simd_dp_1imm_tests.cc - Issue 12223041: Add uses to two ARM tables.

Unified Diff: src/trusted/validator_arm/gen/arm32_decode_simd_dp_1imm_tests.cc

Issue 12223041: Add uses to two ARM tables. (Closed) Base URL: svn://svn.chromium.org/native_client/trunk/src/native_client/

Patch Set: Created 7 years, 10 months ago

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Index: src/trusted/validator_arm/gen/arm32_decode_simd_dp_1imm_tests.cc

===================================================================

--- src/trusted/validator_arm/gen/arm32_decode_simd_dp_1imm_tests.cc (revision 10736)

+++ src/trusted/validator_arm/gen/arm32_decode_simd_dp_1imm_tests.cc (working copy)

@@ -41,6 +41,7 @@

// baseline: Vector1RegisterImmediate_MOV,

// cmode: cmode(11:8),

// constraints: ,

+// defs: {},

// fields: [Vd(15:12), cmode(11:8), Q(6), op(5)],

// generated_baseline: VMOV_immediate_A1_1111001m1d000mmmddddcccc0qp1mmmm_case_0,

// op: op(5),

@@ -50,7 +51,8 @@

// op(5)=1 &&

// cmode(11:8)=~1110 => DECODER_ERROR,

// Q(6)=1 &&

-// Vd(0)=1 => UNDEFINED]}

+// Vd(0)=1 => UNDEFINED],

+// uses: {}}

class Vector1RegisterImmediateTesterCase0

: public Vector1RegisterImmediateTester {

public:

@@ -111,6 +113,9 @@

((((inst.Bits() & 0x0000F000) >> 12) & 0x00000001) ==

0x00000001)));

+ // defs: {};

+ EXPECT_TRUE(decoder.defs(inst).IsSame(RegisterList()));

return true;

}

@@ -121,12 +126,14 @@

// baseline: Vector1RegisterImmediate_BIT,

// cmode: cmode(11:8),

// constraints: ,

+// defs: {},

// fields: [Vd(15:12), cmode(11:8), Q(6)],

// generated_baseline: VORR_immediate_1111001i1d000mmmddddcccc0q01mmmm_case_0,

// safety: [cmode(0)=0 ||

// cmode(3:2)=11 => DECODER_ERROR,

// Q(6)=1 &&

-// Vd(0)=1 => UNDEFINED]}

+// Vd(0)=1 => UNDEFINED],

+// uses: {}}

class Vector1RegisterImmediateTesterCase1

: public Vector1RegisterImmediateTester {

public:

@@ -177,6 +184,9 @@

((((inst.Bits() & 0x0000F000) >> 12) & 0x00000001) ==

0x00000001)));

+ // defs: {};

+ EXPECT_TRUE(decoder.defs(inst).IsSame(RegisterList()));

return true;

}

@@ -187,6 +197,7 @@

// baseline: Vector1RegisterImmediate_MOV,

// cmode: cmode(11:8),

// constraints: ,

+// defs: {},

// fields: [Vd(15:12), cmode(11:8), Q(6), op(5)],

// generated_baseline: VMOV_immediate_A1_1111001m1d000mmmddddcccc0qp1mmmm_case_0,

// op: op(5),

@@ -196,7 +207,8 @@

// op(5)=1 &&

// cmode(11:8)=~1110 => DECODER_ERROR,

// Q(6)=1 &&

-// Vd(0)=1 => UNDEFINED]}

+// Vd(0)=1 => UNDEFINED],

+// uses: {}}

class Vector1RegisterImmediateTesterCase2

: public Vector1RegisterImmediateTester {

public:

@@ -257,6 +269,9 @@

((((inst.Bits() & 0x0000F000) >> 12) & 0x00000001) ==

0x00000001)));

+ // defs: {};

+ EXPECT_TRUE(decoder.defs(inst).IsSame(RegisterList()));

return true;

}

@@ -267,12 +282,14 @@

// baseline: Vector1RegisterImmediate_BIT,

// cmode: cmode(11:8),

// constraints: ,

+// defs: {},

// fields: [Vd(15:12), cmode(11:8), Q(6)],

// generated_baseline: VORR_immediate_1111001i1d000mmmddddcccc0q01mmmm_case_0,

// safety: [cmode(0)=0 ||

// cmode(3:2)=11 => DECODER_ERROR,

// Q(6)=1 &&

-// Vd(0)=1 => UNDEFINED]}

+// Vd(0)=1 => UNDEFINED],

+// uses: {}}

class Vector1RegisterImmediateTesterCase3

: public Vector1RegisterImmediateTester {

public:

@@ -323,6 +340,9 @@

((((inst.Bits() & 0x0000F000) >> 12) & 0x00000001) ==

0x00000001)));

+ // defs: {};

+ EXPECT_TRUE(decoder.defs(inst).IsSame(RegisterList()));

return true;

}

@@ -333,6 +353,7 @@

// baseline: Vector1RegisterImmediate_MOV,

// cmode: cmode(11:8),

// constraints: ,

+// defs: {},

// fields: [Vd(15:12), cmode(11:8), Q(6), op(5)],

// generated_baseline: VMOV_immediate_A1_1111001m1d000mmmddddcccc0qp1mmmm_case_0,

// op: op(5),

@@ -342,7 +363,8 @@

// op(5)=1 &&

// cmode(11:8)=~1110 => DECODER_ERROR,

// Q(6)=1 &&

-// Vd(0)=1 => UNDEFINED]}

+// Vd(0)=1 => UNDEFINED],

+// uses: {}}

class Vector1RegisterImmediateTesterCase4

: public Vector1RegisterImmediateTester {

public:

@@ -403,6 +425,9 @@

((((inst.Bits() & 0x0000F000) >> 12) & 0x00000001) ==

0x00000001)));

+ // defs: {};

+ EXPECT_TRUE(decoder.defs(inst).IsSame(RegisterList()));

return true;

}

@@ -413,6 +438,7 @@

// baseline: Vector1RegisterImmediate_MOV,

// cmode: cmode(11:8),

// constraints: ,

+// defs: {},

// fields: [Vd(15:12), cmode(11:8), Q(6), op(5)],

// generated_baseline: VMOV_immediate_A1_1111001m1d000mmmddddcccc0qp1mmmm_case_0,

// op: op(5),

@@ -422,7 +448,8 @@

// op(5)=1 &&

// cmode(11:8)=~1110 => DECODER_ERROR,

// Q(6)=1 &&

-// Vd(0)=1 => UNDEFINED]}

+// Vd(0)=1 => UNDEFINED],

+// uses: {}}

class Vector1RegisterImmediateTesterCase5

: public Vector1RegisterImmediateTester {

public:

@@ -483,6 +510,9 @@

((((inst.Bits() & 0x0000F000) >> 12) & 0x00000001) ==

0x00000001)));

+ // defs: {};

+ EXPECT_TRUE(decoder.defs(inst).IsSame(RegisterList()));

return true;

}

@@ -493,13 +523,15 @@

// baseline: Vector1RegisterImmediate_MVN,

// cmode: cmode(11:8),

// constraints: ,

+// defs: {},

// fields: [Vd(15:12), cmode(11:8), Q(6)],

// generated_baseline: VMVN_immediate_1111001i1d000mmmddddcccc0q11mmmm_case_0,

// safety: [(cmode(0)=1 &&

// cmode(3:2)=~11) ||

// cmode(3:1)=111 => DECODER_ERROR,

// Q(6)=1 &&

-// Vd(0)=1 => UNDEFINED]}

+// Vd(0)=1 => UNDEFINED],

+// uses: {}}

class Vector1RegisterImmediateTesterCase6

: public Vector1RegisterImmediateTester {

public:

@@ -553,6 +585,9 @@

((((inst.Bits() & 0x0000F000) >> 12) & 0x00000001) ==

0x00000001)));

+ // defs: {};

+ EXPECT_TRUE(decoder.defs(inst).IsSame(RegisterList()));

return true;

}

@@ -563,12 +598,14 @@

// baseline: Vector1RegisterImmediate_BIT,

// cmode: cmode(11:8),

// constraints: ,

+// defs: {},

// fields: [Vd(15:12), cmode(11:8), Q(6)],

// generated_baseline: VBIC_immediate_1111001i1d000mmmddddcccc0q11mmmm_case_0,

// safety: [cmode(0)=0 ||

// cmode(3:2)=11 => DECODER_ERROR,

// Q(6)=1 &&

-// Vd(0)=1 => UNDEFINED]}

+// Vd(0)=1 => UNDEFINED],

+// uses: {}}

class Vector1RegisterImmediateTesterCase7

: public Vector1RegisterImmediateTester {

public:

@@ -619,6 +656,9 @@

((((inst.Bits() & 0x0000F000) >> 12) & 0x00000001) ==

0x00000001)));

+ // defs: {};

+ EXPECT_TRUE(decoder.defs(inst).IsSame(RegisterList()));

return true;

}

@@ -629,13 +669,15 @@

// baseline: Vector1RegisterImmediate_MVN,

// cmode: cmode(11:8),

// constraints: ,

+// defs: {},

// fields: [Vd(15:12), cmode(11:8), Q(6)],

// generated_baseline: VMVN_immediate_1111001i1d000mmmddddcccc0q11mmmm_case_0,

// safety: [(cmode(0)=1 &&

// cmode(3:2)=~11) ||

// cmode(3:1)=111 => DECODER_ERROR,

// Q(6)=1 &&

-// Vd(0)=1 => UNDEFINED]}

+// Vd(0)=1 => UNDEFINED],

+// uses: {}}

class Vector1RegisterImmediateTesterCase8

: public Vector1RegisterImmediateTester {

public:

@@ -689,6 +731,9 @@

((((inst.Bits() & 0x0000F000) >> 12) & 0x00000001) ==

0x00000001)));

+ // defs: {};

+ EXPECT_TRUE(decoder.defs(inst).IsSame(RegisterList()));

return true;

}

@@ -699,13 +744,15 @@

// baseline: Vector1RegisterImmediate_MVN,

// cmode: cmode(11:8),

// constraints: ,

+// defs: {},

// fields: [Vd(15:12), cmode(11:8), Q(6)],

// generated_baseline: VMVN_immediate_1111001i1d000mmmddddcccc0q11mmmm_case_0,

// safety: [(cmode(0)=1 &&

// cmode(3:2)=~11) ||

// cmode(3:1)=111 => DECODER_ERROR,

// Q(6)=1 &&

-// Vd(0)=1 => UNDEFINED]}

+// Vd(0)=1 => UNDEFINED],

+// uses: {}}

class Vector1RegisterImmediateTesterCase9

: public Vector1RegisterImmediateTester {

public:

@@ -759,6 +806,9 @@

((((inst.Bits() & 0x0000F000) >> 12) & 0x00000001) ==

0x00000001)));

+ // defs: {};

+ EXPECT_TRUE(decoder.defs(inst).IsSame(RegisterList()));

return true;

}

@@ -769,12 +819,14 @@

// baseline: Vector1RegisterImmediate_BIT,

// cmode: cmode(11:8),

// constraints: ,

+// defs: {},

// fields: [Vd(15:12), cmode(11:8), Q(6)],

// generated_baseline: VBIC_immediate_1111001i1d000mmmddddcccc0q11mmmm_case_0,

// safety: [cmode(0)=0 ||

// cmode(3:2)=11 => DECODER_ERROR,

// Q(6)=1 &&

-// Vd(0)=1 => UNDEFINED]}

+// Vd(0)=1 => UNDEFINED],

+// uses: {}}

class Vector1RegisterImmediateTesterCase10

: public Vector1RegisterImmediateTester {

public:

@@ -825,6 +877,9 @@

((((inst.Bits() & 0x0000F000) >> 12) & 0x00000001) ==

0x00000001)));

+ // defs: {};

+ EXPECT_TRUE(decoder.defs(inst).IsSame(RegisterList()));

return true;

}

@@ -840,6 +895,7 @@

// baseline: Vector1RegisterImmediate_MOV,

// cmode: cmode(11:8),

// constraints: ,

+// defs: {},

// fields: [Vd(15:12), cmode(11:8), Q(6), op(5)],

// generated_baseline: VMOV_immediate_A1_1111001m1d000mmmddddcccc0qp1mmmm_case_0,

// op: op(5),

@@ -850,7 +906,8 @@

// op(5)=1 &&

// cmode(11:8)=~1110 => DECODER_ERROR,

// Q(6)=1 &&

-// Vd(0)=1 => UNDEFINED]}

+// Vd(0)=1 => UNDEFINED],

+// uses: {}}

class Vector1RegisterImmediate_MOVTester_Case0

: public Vector1RegisterImmediateTesterCase0 {

public:

@@ -867,13 +924,15 @@

// baseline: Vector1RegisterImmediate_BIT,

// cmode: cmode(11:8),

// constraints: ,

+// defs: {},

// fields: [Vd(15:12), cmode(11:8), Q(6)],

// generated_baseline: VORR_immediate_1111001i1d000mmmddddcccc0q01mmmm_case_0,

// rule: VORR_immediate,

// safety: [cmode(0)=0 ||

// cmode(3:2)=11 => DECODER_ERROR,

// Q(6)=1 &&

-// Vd(0)=1 => UNDEFINED]}

+// Vd(0)=1 => UNDEFINED],

+// uses: {}}

class Vector1RegisterImmediate_BITTester_Case1

: public Vector1RegisterImmediateTesterCase1 {

public:

@@ -890,6 +949,7 @@

// baseline: Vector1RegisterImmediate_MOV,

// cmode: cmode(11:8),

// constraints: ,

+// defs: {},

// fields: [Vd(15:12), cmode(11:8), Q(6), op(5)],

// generated_baseline: VMOV_immediate_A1_1111001m1d000mmmddddcccc0qp1mmmm_case_0,

// op: op(5),

@@ -900,7 +960,8 @@

// op(5)=1 &&

// cmode(11:8)=~1110 => DECODER_ERROR,

// Q(6)=1 &&

-// Vd(0)=1 => UNDEFINED]}

+// Vd(0)=1 => UNDEFINED],

+// uses: {}}

class Vector1RegisterImmediate_MOVTester_Case2

: public Vector1RegisterImmediateTesterCase2 {

public:

@@ -917,13 +978,15 @@

// baseline: Vector1RegisterImmediate_BIT,

// cmode: cmode(11:8),

// constraints: ,

+// defs: {},

// fields: [Vd(15:12), cmode(11:8), Q(6)],

// generated_baseline: VORR_immediate_1111001i1d000mmmddddcccc0q01mmmm_case_0,

// rule: VORR_immediate,

// safety: [cmode(0)=0 ||

// cmode(3:2)=11 => DECODER_ERROR,

// Q(6)=1 &&

-// Vd(0)=1 => UNDEFINED]}

+// Vd(0)=1 => UNDEFINED],

+// uses: {}}

class Vector1RegisterImmediate_BITTester_Case3

: public Vector1RegisterImmediateTesterCase3 {

public:

@@ -940,6 +1003,7 @@

// baseline: Vector1RegisterImmediate_MOV,

// cmode: cmode(11:8),

// constraints: ,

+// defs: {},

// fields: [Vd(15:12), cmode(11:8), Q(6), op(5)],

// generated_baseline: VMOV_immediate_A1_1111001m1d000mmmddddcccc0qp1mmmm_case_0,

// op: op(5),

@@ -950,7 +1014,8 @@

// op(5)=1 &&

// cmode(11:8)=~1110 => DECODER_ERROR,

// Q(6)=1 &&

-// Vd(0)=1 => UNDEFINED]}

+// Vd(0)=1 => UNDEFINED],

+// uses: {}}

class Vector1RegisterImmediate_MOVTester_Case4

: public Vector1RegisterImmediateTesterCase4 {

public:

@@ -967,6 +1032,7 @@

// baseline: Vector1RegisterImmediate_MOV,

// cmode: cmode(11:8),

// constraints: ,

+// defs: {},

// fields: [Vd(15:12), cmode(11:8), Q(6), op(5)],

// generated_baseline: VMOV_immediate_A1_1111001m1d000mmmddddcccc0qp1mmmm_case_0,

// op: op(5),

@@ -977,7 +1043,8 @@

// op(5)=1 &&

// cmode(11:8)=~1110 => DECODER_ERROR,

// Q(6)=1 &&

-// Vd(0)=1 => UNDEFINED]}

+// Vd(0)=1 => UNDEFINED],

+// uses: {}}

class Vector1RegisterImmediate_MOVTester_Case5

: public Vector1RegisterImmediateTesterCase5 {

public:

@@ -994,6 +1061,7 @@

// baseline: Vector1RegisterImmediate_MVN,

// cmode: cmode(11:8),

// constraints: ,

+// defs: {},

// fields: [Vd(15:12), cmode(11:8), Q(6)],

// generated_baseline: VMVN_immediate_1111001i1d000mmmddddcccc0q11mmmm_case_0,

// rule: VMVN_immediate,

@@ -1001,7 +1069,8 @@

// cmode(3:2)=~11) ||

// cmode(3:1)=111 => DECODER_ERROR,

// Q(6)=1 &&

-// Vd(0)=1 => UNDEFINED]}

+// Vd(0)=1 => UNDEFINED],

+// uses: {}}

class Vector1RegisterImmediate_MVNTester_Case6

: public Vector1RegisterImmediateTesterCase6 {

public:

@@ -1018,13 +1087,15 @@

// baseline: Vector1RegisterImmediate_BIT,

// cmode: cmode(11:8),

// constraints: ,

+// defs: {},

// fields: [Vd(15:12), cmode(11:8), Q(6)],

// generated_baseline: VBIC_immediate_1111001i1d000mmmddddcccc0q11mmmm_case_0,

// rule: VBIC_immediate,

// safety: [cmode(0)=0 ||

// cmode(3:2)=11 => DECODER_ERROR,

// Q(6)=1 &&

-// Vd(0)=1 => UNDEFINED]}

+// Vd(0)=1 => UNDEFINED],

+// uses: {}}

class Vector1RegisterImmediate_BITTester_Case7

: public Vector1RegisterImmediateTesterCase7 {

public:

@@ -1041,6 +1112,7 @@

// baseline: Vector1RegisterImmediate_MVN,

// cmode: cmode(11:8),

// constraints: ,

+// defs: {},

// fields: [Vd(15:12), cmode(11:8), Q(6)],

// generated_baseline: VMVN_immediate_1111001i1d000mmmddddcccc0q11mmmm_case_0,

// rule: VMVN_immediate,

@@ -1048,7 +1120,8 @@

// cmode(3:2)=~11) ||

// cmode(3:1)=111 => DECODER_ERROR,

// Q(6)=1 &&

-// Vd(0)=1 => UNDEFINED]}

+// Vd(0)=1 => UNDEFINED],

+// uses: {}}

class Vector1RegisterImmediate_MVNTester_Case8

: public Vector1RegisterImmediateTesterCase8 {

public:

@@ -1065,6 +1138,7 @@

// baseline: Vector1RegisterImmediate_MVN,

// cmode: cmode(11:8),

// constraints: ,

+// defs: {},

// fields: [Vd(15:12), cmode(11:8), Q(6)],

// generated_baseline: VMVN_immediate_1111001i1d000mmmddddcccc0q11mmmm_case_0,

// rule: VMVN_immediate,

@@ -1072,7 +1146,8 @@

// cmode(3:2)=~11) ||

// cmode(3:1)=111 => DECODER_ERROR,

// Q(6)=1 &&

-// Vd(0)=1 => UNDEFINED]}

+// Vd(0)=1 => UNDEFINED],

+// uses: {}}

class Vector1RegisterImmediate_MVNTester_Case9

: public Vector1RegisterImmediateTesterCase9 {

public:

@@ -1089,13 +1164,15 @@

// baseline: Vector1RegisterImmediate_BIT,

// cmode: cmode(11:8),

// constraints: ,

+// defs: {},

// fields: [Vd(15:12), cmode(11:8), Q(6)],

// generated_baseline: VBIC_immediate_1111001i1d000mmmddddcccc0q11mmmm_case_0,

// rule: VBIC_immediate,

// safety: [cmode(0)=0 ||

// cmode(3:2)=11 => DECODER_ERROR,

// Q(6)=1 &&

-// Vd(0)=1 => UNDEFINED]}

+// Vd(0)=1 => UNDEFINED],

+// uses: {}}

class Vector1RegisterImmediate_BITTester_Case10

: public Vector1RegisterImmediateTesterCase10 {

public:

@@ -1121,6 +1198,7 @@

// baseline: Vector1RegisterImmediate_MOV,

// cmode: cmode(11:8),

// constraints: ,

+// defs: {},

// fields: [Vd(15:12), cmode(11:8), Q(6), op(5)],

// generated_baseline: VMOV_immediate_A1_1111001m1d000mmmddddcccc0qp1mmmm_case_0,

// op: op(5),

@@ -1132,7 +1210,8 @@

// op(5)=1 &&

// cmode(11:8)=~1110 => DECODER_ERROR,

// Q(6)=1 &&

-// Vd(0)=1 => UNDEFINED]}

+// Vd(0)=1 => UNDEFINED],

+// uses: {}}

TEST_F(Arm32DecoderStateTests,

Vector1RegisterImmediate_MOVTester_Case0_TestCase0) {

Vector1RegisterImmediate_MOVTester_Case0 tester;

@@ -1146,6 +1225,7 @@

// baseline: Vector1RegisterImmediate_BIT,

// cmode: cmode(11:8),

// constraints: ,

+// defs: {},

// fields: [Vd(15:12), cmode(11:8), Q(6)],

// generated_baseline: VORR_immediate_1111001i1d000mmmddddcccc0q01mmmm_case_0,

// pattern: 1111001i1d000mmmddddcccc0q01mmmm,

@@ -1153,7 +1233,8 @@

// safety: [cmode(0)=0 ||

// cmode(3:2)=11 => DECODER_ERROR,

// Q(6)=1 &&

-// Vd(0)=1 => UNDEFINED]}

+// Vd(0)=1 => UNDEFINED],

+// uses: {}}

TEST_F(Arm32DecoderStateTests,

Vector1RegisterImmediate_BITTester_Case1_TestCase1) {

Vector1RegisterImmediate_BITTester_Case1 tester;

@@ -1167,6 +1248,7 @@

// baseline: Vector1RegisterImmediate_MOV,

// cmode: cmode(11:8),

// constraints: ,

+// defs: {},

// fields: [Vd(15:12), cmode(11:8), Q(6), op(5)],

// generated_baseline: VMOV_immediate_A1_1111001m1d000mmmddddcccc0qp1mmmm_case_0,

// op: op(5),

@@ -1178,7 +1260,8 @@

// op(5)=1 &&

// cmode(11:8)=~1110 => DECODER_ERROR,

// Q(6)=1 &&

-// Vd(0)=1 => UNDEFINED]}

+// Vd(0)=1 => UNDEFINED],

+// uses: {}}

TEST_F(Arm32DecoderStateTests,

Vector1RegisterImmediate_MOVTester_Case2_TestCase2) {

Vector1RegisterImmediate_MOVTester_Case2 tester;

@@ -1192,6 +1275,7 @@

// baseline: Vector1RegisterImmediate_BIT,

// cmode: cmode(11:8),

// constraints: ,

+// defs: {},

// fields: [Vd(15:12), cmode(11:8), Q(6)],

// generated_baseline: VORR_immediate_1111001i1d000mmmddddcccc0q01mmmm_case_0,

// pattern: 1111001i1d000mmmddddcccc0q01mmmm,

@@ -1199,7 +1283,8 @@

// safety: [cmode(0)=0 ||

// cmode(3:2)=11 => DECODER_ERROR,

// Q(6)=1 &&

-// Vd(0)=1 => UNDEFINED]}

+// Vd(0)=1 => UNDEFINED],

+// uses: {}}

TEST_F(Arm32DecoderStateTests,

Vector1RegisterImmediate_BITTester_Case3_TestCase3) {

Vector1RegisterImmediate_BITTester_Case3 tester;

@@ -1213,6 +1298,7 @@

// baseline: Vector1RegisterImmediate_MOV,

// cmode: cmode(11:8),

// constraints: ,

+// defs: {},

// fields: [Vd(15:12), cmode(11:8), Q(6), op(5)],

// generated_baseline: VMOV_immediate_A1_1111001m1d000mmmddddcccc0qp1mmmm_case_0,

// op: op(5),

@@ -1224,7 +1310,8 @@

// op(5)=1 &&

// cmode(11:8)=~1110 => DECODER_ERROR,

// Q(6)=1 &&

-// Vd(0)=1 => UNDEFINED]}

+// Vd(0)=1 => UNDEFINED],

+// uses: {}}

TEST_F(Arm32DecoderStateTests,

Vector1RegisterImmediate_MOVTester_Case4_TestCase4) {

Vector1RegisterImmediate_MOVTester_Case4 tester;

@@ -1238,6 +1325,7 @@

// baseline: Vector1RegisterImmediate_MOV,

// cmode: cmode(11:8),

// constraints: ,

+// defs: {},

// fields: [Vd(15:12), cmode(11:8), Q(6), op(5)],

// generated_baseline: VMOV_immediate_A1_1111001m1d000mmmddddcccc0qp1mmmm_case_0,

// op: op(5),

@@ -1249,7 +1337,8 @@

// op(5)=1 &&

// cmode(11:8)=~1110 => DECODER_ERROR,

// Q(6)=1 &&

-// Vd(0)=1 => UNDEFINED]}

+// Vd(0)=1 => UNDEFINED],

+// uses: {}}

TEST_F(Arm32DecoderStateTests,

Vector1RegisterImmediate_MOVTester_Case5_TestCase5) {

Vector1RegisterImmediate_MOVTester_Case5 tester;

@@ -1263,6 +1352,7 @@

// baseline: Vector1RegisterImmediate_MVN,

// cmode: cmode(11:8),

// constraints: ,

+// defs: {},

// fields: [Vd(15:12), cmode(11:8), Q(6)],

// generated_baseline: VMVN_immediate_1111001i1d000mmmddddcccc0q11mmmm_case_0,

// pattern: 1111001i1d000mmmddddcccc0q11mmmm,

@@ -1271,7 +1361,8 @@

// cmode(3:2)=~11) ||

// cmode(3:1)=111 => DECODER_ERROR,

// Q(6)=1 &&

-// Vd(0)=1 => UNDEFINED]}

+// Vd(0)=1 => UNDEFINED],

+// uses: {}}

TEST_F(Arm32DecoderStateTests,

Vector1RegisterImmediate_MVNTester_Case6_TestCase6) {

Vector1RegisterImmediate_MVNTester_Case6 tester;

@@ -1285,6 +1376,7 @@

// baseline: Vector1RegisterImmediate_BIT,

// cmode: cmode(11:8),

// constraints: ,

+// defs: {},

// fields: [Vd(15:12), cmode(11:8), Q(6)],

// generated_baseline: VBIC_immediate_1111001i1d000mmmddddcccc0q11mmmm_case_0,

// pattern: 1111001i1d000mmmddddcccc0q11mmmm,

@@ -1292,7 +1384,8 @@

// safety: [cmode(0)=0 ||

// cmode(3:2)=11 => DECODER_ERROR,

// Q(6)=1 &&

-// Vd(0)=1 => UNDEFINED]}

+// Vd(0)=1 => UNDEFINED],

+// uses: {}}

TEST_F(Arm32DecoderStateTests,

Vector1RegisterImmediate_BITTester_Case7_TestCase7) {

Vector1RegisterImmediate_BITTester_Case7 tester;

@@ -1306,6 +1399,7 @@

// baseline: Vector1RegisterImmediate_MVN,

// cmode: cmode(11:8),

// constraints: ,

+// defs: {},

// fields: [Vd(15:12), cmode(11:8), Q(6)],

// generated_baseline: VMVN_immediate_1111001i1d000mmmddddcccc0q11mmmm_case_0,

// pattern: 1111001i1d000mmmddddcccc0q11mmmm,

@@ -1314,7 +1408,8 @@

// cmode(3:2)=~11) ||

// cmode(3:1)=111 => DECODER_ERROR,

// Q(6)=1 &&

-// Vd(0)=1 => UNDEFINED]}

+// Vd(0)=1 => UNDEFINED],

+// uses: {}}

TEST_F(Arm32DecoderStateTests,

Vector1RegisterImmediate_MVNTester_Case8_TestCase8) {

Vector1RegisterImmediate_MVNTester_Case8 tester;

@@ -1328,6 +1423,7 @@

// baseline: Vector1RegisterImmediate_MVN,

// cmode: cmode(11:8),

// constraints: ,

+// defs: {},

// fields: [Vd(15:12), cmode(11:8), Q(6)],

// generated_baseline: VMVN_immediate_1111001i1d000mmmddddcccc0q11mmmm_case_0,

// pattern: 1111001i1d000mmmddddcccc0q11mmmm,

@@ -1336,7 +1432,8 @@

// cmode(3:2)=~11) ||

// cmode(3:1)=111 => DECODER_ERROR,

// Q(6)=1 &&

-// Vd(0)=1 => UNDEFINED]}

+// Vd(0)=1 => UNDEFINED],

+// uses: {}}

TEST_F(Arm32DecoderStateTests,

Vector1RegisterImmediate_MVNTester_Case9_TestCase9) {

Vector1RegisterImmediate_MVNTester_Case9 tester;

@@ -1350,6 +1447,7 @@

// baseline: Vector1RegisterImmediate_BIT,

// cmode: cmode(11:8),

// constraints: ,

+// defs: {},

// fields: [Vd(15:12), cmode(11:8), Q(6)],

// generated_baseline: VBIC_immediate_1111001i1d000mmmddddcccc0q11mmmm_case_0,

// pattern: 1111001i1d000mmmddddcccc0q11mmmm,

@@ -1357,7 +1455,8 @@

// safety: [cmode(0)=0 ||

// cmode(3:2)=11 => DECODER_ERROR,

// Q(6)=1 &&

-// Vd(0)=1 => UNDEFINED]}

+// Vd(0)=1 => UNDEFINED],

+// uses: {}}

TEST_F(Arm32DecoderStateTests,

Vector1RegisterImmediate_BITTester_Case10_TestCase10) {

Vector1RegisterImmediate_BITTester_Case10 tester;

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