Add uses to two ARM tables.

src/trusted/validator_arm/gen/arm32_decode_baselines_3.h

 /*
  * Copyright 2013 The Native Client Authors.  All rights reserved.
  * Use of this source code is governed by a BSD-style license that can
  * be found in the LICENSE file.
  */
 
 // DO NOT EDIT: GENERATED CODE
 
 #ifndef NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_GEN_ARM32_DECODE_BASELINES_3_H_
 #define NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_GEN_ARM32_DECODE_BASELINES_3_H_
@@ skipping 2423 matching lines @@
 // VMOV_immediate_A1_1111001m1d000mmmddddcccc0qp1mmmm_case_0:
 //
 //   {D: D(22),
 //    Q: Q(6),
 //    Vd: Vd(15:12),
 //    arch: ASIMD,
 //    baseline: Vector1RegisterImmediate_MOV,
 //    cmode: cmode(11:8),
 //    constraints: ,
 //    d: D:Vd,
+//    defs: {},
 //    false: false,
 //    fields: [i(24),
 //      D(22),
 //      imm3(18:16),
 //      Vd(15:12),
 //      cmode(11:8),
 //      Q(6),
 //      op(5),
 //      imm4(3:0)],
 //    generated_baseline: VMOV_immediate_A1_1111001m1d000mmmddddcccc0qp1mmmm_case_0,
 //    i: i(24),
 //    imm3: imm3(18:16),
 //    imm4: imm4(3:0),
 //    imm64: AdvSIMDExpandImm(op, cmode, i:imm3:imm4),
 //    op: op(5),
 //    pattern: 1111001m1d000mmmddddcccc0qp1mmmm,
 //    regs: 1
 //         if Q(6)=0
 //         else 2,
 //    rule: VMOV_immediate_A1,
 //    safety: [op(5)=0 &&
 //         cmode(0)=1 &&
 //         cmode(3:2)=~11 => DECODER_ERROR,
 //      op(5)=1 &&
 //         cmode(11:8)=~1110 => DECODER_ERROR,
 //      Q(6)=1 &&
 //         Vd(0)=1 => UNDEFINED],
-//    single_register: false}
+//    single_register: false,
+//    uses: {}}
 class VMOV_immediate_A1_1111001m1d000mmmddddcccc0qp1mmmm_case_0
      : public ClassDecoder {
  public:
   VMOV_immediate_A1_1111001m1d000mmmddddcccc0qp1mmmm_case_0()
      : ClassDecoder() {}
+  virtual RegisterList defs(Instruction inst) const;
   virtual SafetyLevel safety(Instruction i) const;
+  virtual RegisterList uses(Instruction i) const;
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(
       VMOV_immediate_A1_1111001m1d000mmmddddcccc0qp1mmmm_case_0);
 };
 
 // VMOV_immediate_cccc11101d11iiiidddd101s0000iiii_case_0:
 //
 //   {D: D(22),
 //    Vd: Vd(15:12),
 //    advsimd: false,
@@ skipping 639 matching lines @@
 // VMVN_immediate_1111001i1d000mmmddddcccc0q11mmmm_case_0:
 //
 //   {D: D(22),
 //    Q: Q(6),
 //    Vd: Vd(15:12),
 //    arch: ASIMD,
 //    baseline: Vector1RegisterImmediate_MVN,
 //    cmode: cmode(11:8),
 //    constraints: ,
 //    d: D:Vd,
+//    defs: {},
 //    fields: [i(24),
 //      D(22),
 //      imm3(18:16),
 //      Vd(15:12),
 //      cmode(11:8),
 //      Q(6),
 //      op(5),
 //      imm4(3:0)],
 //    generated_baseline: VMVN_immediate_1111001i1d000mmmddddcccc0q11mmmm_case_0,
 //    i: i(24),
 //    imm3: imm3(18:16),
 //    imm4: imm4(3:0),
 //    imm64: AdvSIMDExpandImm(op, cmode, i:imm3:imm4),
 //    op: op(5),
 //    pattern: 1111001i1d000mmmddddcccc0q11mmmm,
 //    regs: 1
 //         if Q(6)=0
 //         else 2,
 //    rule: VMVN_immediate,
 //    safety: [(cmode(0)=1 &&
 //         cmode(3:2)=~11) ||
 //         cmode(3:1)=111 => DECODER_ERROR,
 //      Q(6)=1 &&
-//         Vd(0)=1 => UNDEFINED]}
+//         Vd(0)=1 => UNDEFINED],
+//    uses: {}}
 class VMVN_immediate_1111001i1d000mmmddddcccc0q11mmmm_case_0
      : public ClassDecoder {
  public:
   VMVN_immediate_1111001i1d000mmmddddcccc0q11mmmm_case_0()
      : ClassDecoder() {}
+  virtual RegisterList defs(Instruction inst) const;
   virtual SafetyLevel safety(Instruction i) const;
+  virtual RegisterList uses(Instruction i) const;
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(
       VMVN_immediate_1111001i1d000mmmddddcccc0q11mmmm_case_0);
 };
 
 // VMVN_register_111100111d11ss00dddd01011qm0mmmm_case_0:
 //
 //   {D: D(22),
 //    F: F(10),
 //    M: M(5),
@@ skipping 348 matching lines @@
 // VORR_immediate_1111001i1d000mmmddddcccc0q01mmmm_case_0:
 //
 //   {D: D(22),
 //    Q: Q(6),
 //    Vd: Vd(15:12),
 //    arch: ASIMD,
 //    baseline: Vector1RegisterImmediate_BIT,
 //    cmode: cmode(11:8),
 //    constraints: ,
 //    d: D:Vd,
+//    defs: {},
 //    fields: [i(24),
 //      D(22),
 //      imm3(18:16),
 //      Vd(15:12),
 //      cmode(11:8),
 //      Q(6),
 //      op(5),
 //      imm4(3:0)],
 //    generated_baseline: VORR_immediate_1111001i1d000mmmddddcccc0q01mmmm_case_0,
 //    i: i(24),
 //    imm3: imm3(18:16),
 //    imm4: imm4(3:0),
 //    imm64: AdvSIMDExpandImm(op, cmode, i:imm3:imm4),
 //    op: op(5),
 //    pattern: 1111001i1d000mmmddddcccc0q01mmmm,
 //    regs: 1
 //         if Q(6)=0
 //         else 2,
 //    rule: VORR_immediate,
 //    safety: [cmode(0)=0 ||
 //         cmode(3:2)=11 => DECODER_ERROR,
 //      Q(6)=1 &&
-//         Vd(0)=1 => UNDEFINED]}
+//         Vd(0)=1 => UNDEFINED],
+//    uses: {}}
 class VORR_immediate_1111001i1d000mmmddddcccc0q01mmmm_case_0
      : public ClassDecoder {
  public:
   VORR_immediate_1111001i1d000mmmddddcccc0q01mmmm_case_0()
      : ClassDecoder() {}
+  virtual RegisterList defs(Instruction inst) const;
   virtual SafetyLevel safety(Instruction i) const;
+  virtual RegisterList uses(Instruction i) const;
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(
       VORR_immediate_1111001i1d000mmmddddcccc0q01mmmm_case_0);
 };
 
 // VORR_register_or_VMOV_register_A1_111100100d10nnnndddd0001nqm1mmmm_case_0:
 //
 //   {D: D(22),
 //    M: M(5),
 //    N: N(7),
@@ skipping 5004 matching lines @@
   virtual SafetyLevel safety(Instruction i) const;
   virtual RegisterList uses(Instruction i) const;
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(
       YIELD_cccc0011001000001111000000000001_case_0);
 };
 
 } // namespace nacl_arm_test
 
 #endif  // NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_GEN_ARM32_DECODE_BASELINES_3_H_