Add uses to two ARM tables.

src/trusted/validator_arm/gen/arm32_decode_baselines_3.cc

 /*
  * Copyright 2013 The Native Client Authors.  All rights reserved.
  * Use of this source code is governed by a BSD-style license that can
  * be found in the LICENSE file.
  */
 
 // DO NOT EDIT: GENERATED CODE
 
 #include "native_client/src/trusted/validator_arm/gen/arm32_decode_baselines.h"
 #include "native_client/src/trusted/validator_arm/inst_classes.h"
@@ skipping 4260 matching lines @@
 // VMOV_immediate_A1_1111001m1d000mmmddddcccc0qp1mmmm_case_0:
 //
 //   {D: D(22),
 //    Q: Q(6),
 //    Vd: Vd(15:12),
 //    arch: ASIMD,
 //    baseline: Vector1RegisterImmediate_MOV,
 //    cmode: cmode(11:8),
 //    constraints: ,
 //    d: D:Vd,
+//    defs: {},
 //    false: false,
 //    fields: [i(24),
 //      D(22),
 //      imm3(18:16),
 //      Vd(15:12),
 //      cmode(11:8),
 //      Q(6),
 //      op(5),
 //      imm4(3:0)],
 //    generated_baseline: VMOV_immediate_A1_1111001m1d000mmmddddcccc0qp1mmmm_case_0,
 //    i: i(24),
 //    imm3: imm3(18:16),
 //    imm4: imm4(3:0),
 //    imm64: AdvSIMDExpandImm(op, cmode, i:imm3:imm4),
 //    op: op(5),
 //    pattern: 1111001m1d000mmmddddcccc0qp1mmmm,
 //    regs: 1
 //         if Q(6)=0
 //         else 2,
 //    rule: VMOV_immediate_A1,
 //    safety: [op(5)=0 &&
 //         cmode(0)=1 &&
 //         cmode(3:2)=~11 => DECODER_ERROR,
 //      op(5)=1 &&
 //         cmode(11:8)=~1110 => DECODER_ERROR,
 //      Q(6)=1 &&
 //         Vd(0)=1 => UNDEFINED],
-//    single_register: false}
+//    single_register: false,
+//    uses: {}}
+RegisterList VMOV_immediate_A1_1111001m1d000mmmddddcccc0qp1mmmm_case_0::
+defs(Instruction inst) const {
+  UNREFERENCED_PARAMETER(inst);  // To silence compiler.
+  // defs: '{}'
+  return RegisterList();
+}
+
 SafetyLevel VMOV_immediate_A1_1111001m1d000mmmddddcccc0qp1mmmm_case_0::
 safety(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
 
   // inst(5)=0 &&
   //       inst(11:8)(0)=1 &&
   //       inst(11:8)(3:2)=~11 => DECODER_ERROR
   if (((inst.Bits() & 0x00000020)  ==
           0x00000000) &&
        ((((inst.Bits() & 0x00000F00) >> 8) & 0x00000001)  ==
@@ skipping 15 matching lines @@
   if (((inst.Bits() & 0x00000040)  ==
           0x00000040) &&
        ((((inst.Bits() & 0x0000F000) >> 12) & 0x00000001)  ==
           0x00000001))
     return UNDEFINED;
 
   return MAY_BE_SAFE;
 }
 
 
+RegisterList VMOV_immediate_A1_1111001m1d000mmmddddcccc0qp1mmmm_case_0::
+uses(Instruction inst) const {
+  UNREFERENCED_PARAMETER(inst);  // To silence compiler.
+  // uses: '{}'
+  return RegisterList();
+}
+
 // VMOV_immediate_cccc11101d11iiiidddd101s0000iiii_case_0:
 //
 //   {D: D(22),
 //    Vd: Vd(15:12),
 //    advsimd: false,
 //    arch: VFPv3,
 //    baseline: CondVfpOp,
 //    cond: cond(31:28),
 //    constraints: ,
 //    d: Vd:D
@@ skipping 913 matching lines @@
 // VMVN_immediate_1111001i1d000mmmddddcccc0q11mmmm_case_0:
 //
 //   {D: D(22),
 //    Q: Q(6),
 //    Vd: Vd(15:12),
 //    arch: ASIMD,
 //    baseline: Vector1RegisterImmediate_MVN,
 //    cmode: cmode(11:8),
 //    constraints: ,
 //    d: D:Vd,
+//    defs: {},
 //    fields: [i(24),
 //      D(22),
 //      imm3(18:16),
 //      Vd(15:12),
 //      cmode(11:8),
 //      Q(6),
 //      op(5),
 //      imm4(3:0)],
 //    generated_baseline: VMVN_immediate_1111001i1d000mmmddddcccc0q11mmmm_case_0,
 //    i: i(24),
 //    imm3: imm3(18:16),
 //    imm4: imm4(3:0),
 //    imm64: AdvSIMDExpandImm(op, cmode, i:imm3:imm4),
 //    op: op(5),
 //    pattern: 1111001i1d000mmmddddcccc0q11mmmm,
 //    regs: 1
 //         if Q(6)=0
 //         else 2,
 //    rule: VMVN_immediate,
 //    safety: [(cmode(0)=1 &&
 //         cmode(3:2)=~11) ||
 //         cmode(3:1)=111 => DECODER_ERROR,
 //      Q(6)=1 &&
-//         Vd(0)=1 => UNDEFINED]}
+//         Vd(0)=1 => UNDEFINED],
+//    uses: {}}
+RegisterList VMVN_immediate_1111001i1d000mmmddddcccc0q11mmmm_case_0::
+defs(Instruction inst) const {
+  UNREFERENCED_PARAMETER(inst);  // To silence compiler.
+  // defs: '{}'
+  return RegisterList();
+}
+
 SafetyLevel VMVN_immediate_1111001i1d000mmmddddcccc0q11mmmm_case_0::
 safety(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
 
   // (inst(11:8)(0)=1 &&
   //       inst(11:8)(3:2)=~11) ||
   //       inst(11:8)(3:1)=111 => DECODER_ERROR
   if (((((((inst.Bits() & 0x00000F00) >> 8) & 0x00000001)  ==
           0x00000001) &&
        ((((inst.Bits() & 0x00000F00) >> 8) & 0x0000000C)  !=
           0x0000000C))) ||
        ((((inst.Bits() & 0x00000F00) >> 8) & 0x0000000E)  ==
           0x0000000E))
     return DECODER_ERROR;
 
   // inst(6)=1 &&
   //       inst(15:12)(0)=1 => UNDEFINED
   if (((inst.Bits() & 0x00000040)  ==
           0x00000040) &&
        ((((inst.Bits() & 0x0000F000) >> 12) & 0x00000001)  ==
           0x00000001))
     return UNDEFINED;
 
   return MAY_BE_SAFE;
 }
 
 
+RegisterList VMVN_immediate_1111001i1d000mmmddddcccc0q11mmmm_case_0::
+uses(Instruction inst) const {
+  UNREFERENCED_PARAMETER(inst);  // To silence compiler.
+  // uses: '{}'
+  return RegisterList();
+}
+
 // VMVN_register_111100111d11ss00dddd01011qm0mmmm_case_0:
 //
 //   {D: D(22),
 //    F: F(10),
 //    M: M(5),
 //    Q: Q(6),
 //    Vd: Vd(15:12),
 //    Vm: Vm(3:0),
 //    arch: ASIMD,
 //    baseline: Vector2RegisterMiscellaneous_V8,
@@ skipping 482 matching lines @@
 // VORR_immediate_1111001i1d000mmmddddcccc0q01mmmm_case_0:
 //
 //   {D: D(22),
 //    Q: Q(6),
 //    Vd: Vd(15:12),
 //    arch: ASIMD,
 //    baseline: Vector1RegisterImmediate_BIT,
 //    cmode: cmode(11:8),
 //    constraints: ,
 //    d: D:Vd,
+//    defs: {},
 //    fields: [i(24),
 //      D(22),
 //      imm3(18:16),
 //      Vd(15:12),
 //      cmode(11:8),
 //      Q(6),
 //      op(5),
 //      imm4(3:0)],
 //    generated_baseline: VORR_immediate_1111001i1d000mmmddddcccc0q01mmmm_case_0,
 //    i: i(24),
 //    imm3: imm3(18:16),
 //    imm4: imm4(3:0),
 //    imm64: AdvSIMDExpandImm(op, cmode, i:imm3:imm4),
 //    op: op(5),
 //    pattern: 1111001i1d000mmmddddcccc0q01mmmm,
 //    regs: 1
 //         if Q(6)=0
 //         else 2,
 //    rule: VORR_immediate,
 //    safety: [cmode(0)=0 ||
 //         cmode(3:2)=11 => DECODER_ERROR,
 //      Q(6)=1 &&
-//         Vd(0)=1 => UNDEFINED]}
+//         Vd(0)=1 => UNDEFINED],
+//    uses: {}}
+RegisterList VORR_immediate_1111001i1d000mmmddddcccc0q01mmmm_case_0::
+defs(Instruction inst) const {
+  UNREFERENCED_PARAMETER(inst);  // To silence compiler.
+  // defs: '{}'
+  return RegisterList();
+}
+
 SafetyLevel VORR_immediate_1111001i1d000mmmddddcccc0q01mmmm_case_0::
 safety(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
 
   // inst(11:8)(0)=0 ||
   //       inst(11:8)(3:2)=11 => DECODER_ERROR
   if (((((inst.Bits() & 0x00000F00) >> 8) & 0x00000001)  ==
           0x00000000) ||
        ((((inst.Bits() & 0x00000F00) >> 8) & 0x0000000C)  ==
           0x0000000C))
     return DECODER_ERROR;
 
   // inst(6)=1 &&
   //       inst(15:12)(0)=1 => UNDEFINED
   if (((inst.Bits() & 0x00000040)  ==
           0x00000040) &&
        ((((inst.Bits() & 0x0000F000) >> 12) & 0x00000001)  ==
           0x00000001))
     return UNDEFINED;
 
   return MAY_BE_SAFE;
 }
 
 
+RegisterList VORR_immediate_1111001i1d000mmmddddcccc0q01mmmm_case_0::
+uses(Instruction inst) const {
+  UNREFERENCED_PARAMETER(inst);  // To silence compiler.
+  // uses: '{}'
+  return RegisterList();
+}
+
 // VORR_register_or_VMOV_register_A1_111100100d10nnnndddd0001nqm1mmmm_case_0:
 //
 //   {D: D(22),
 //    M: M(5),
 //    N: N(7),
 //    Q: Q(6),
 //    U: U(24),
 //    Vd: Vd(15:12),
 //    Vm: Vm(3:0),
 //    Vn: Vn(19:16),
@@ skipping 7726 matching lines @@
 
 
 RegisterList YIELD_cccc0011001000001111000000000001_case_0::
 uses(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
   // uses: '{}'
   return RegisterList();
 }
 
 }  // namespace nacl_arm_dec