Add uses to two ARM tables.

src/trusted/validator_arm/gen/arm32_decode_actuals_2.h

 /*
  * Copyright 2013 The Native Client Authors.  All rights reserved.
  * Use of this source code is governed by a BSD-style license that can
  * be found in the LICENSE file.
  */
 
 // DO NOT EDIT: GENERATED CODE
 
 #ifndef NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_GEN_ARM32_DECODE_ACTUALS_2_H_
 #define NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_GEN_ARM32_DECODE_ACTUALS_2_H_
@@ skipping 3240 matching lines @@
   virtual SafetyLevel safety(Instruction i) const;
   virtual RegisterList uses(Instruction i) const;
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(
       Actual_VADD_integer_111100100dssnnnndddd1000nqm0mmmm_case_1);
 };
 
 // Actual_VBIC_immediate_1111001i1d000mmmddddcccc0q11mmmm_case_1
 //
 // Actual:
-//   {safety: [inst(11:8)(0)=0 ||
+//   {defs: {},
+//    safety: [inst(11:8)(0)=0 ||
 //         inst(11:8)(3:2)=11 => DECODER_ERROR,
 //      inst(6)=1 &&
-//         inst(15:12)(0)=1 => UNDEFINED]}
+//         inst(15:12)(0)=1 => UNDEFINED],
+//    uses: {}}
 //
 // Baseline:
 //   {D: D(22),
 //    Q: Q(6),
 //    Vd: Vd(15:12),
 //    arch: ASIMD,
 //    baseline: Vector1RegisterImmediate_BIT,
 //    cmode: cmode(11:8),
 //    constraints: ,
 //    d: D:Vd,
+//    defs: {},
 //    fields: [i(24),
 //      D(22),
 //      imm3(18:16),
 //      Vd(15:12),
 //      cmode(11:8),
 //      Q(6),
 //      op(5),
 //      imm4(3:0)],
 //    generated_baseline: VBIC_immediate_1111001i1d000mmmddddcccc0q11mmmm_case_0,
 //    i: i(24),
 //    imm3: imm3(18:16),
 //    imm4: imm4(3:0),
 //    imm64: AdvSIMDExpandImm(op, cmode, i:imm3:imm4),
 //    op: op(5),
 //    pattern: 1111001i1d000mmmddddcccc0q11mmmm,
 //    regs: 1
 //         if Q(6)=0
 //         else 2,
 //    rule: VBIC_immediate,
 //    safety: [cmode(0)=0 ||
 //         cmode(3:2)=11 => DECODER_ERROR,
 //      Q(6)=1 &&
-//         Vd(0)=1 => UNDEFINED]}
+//         Vd(0)=1 => UNDEFINED],
+//    uses: {}}
 //
 // Baseline:
 //   {D: D(22),
 //    Q: Q(6),
 //    Vd: Vd(15:12),
 //    arch: ASIMD,
 //    baseline: Vector1RegisterImmediate_BIT,
 //    cmode: cmode(11:8),
 //    constraints: ,
 //    d: D:Vd,
+//    defs: {},
 //    fields: [i(24),
 //      D(22),
 //      imm3(18:16),
 //      Vd(15:12),
 //      cmode(11:8),
 //      Q(6),
 //      op(5),
 //      imm4(3:0)],
 //    generated_baseline: VORR_immediate_1111001i1d000mmmddddcccc0q01mmmm_case_0,
 //    i: i(24),
 //    imm3: imm3(18:16),
 //    imm4: imm4(3:0),
 //    imm64: AdvSIMDExpandImm(op, cmode, i:imm3:imm4),
 //    op: op(5),
 //    pattern: 1111001i1d000mmmddddcccc0q01mmmm,
 //    regs: 1
 //         if Q(6)=0
 //         else 2,
 //    rule: VORR_immediate,
 //    safety: [cmode(0)=0 ||
 //         cmode(3:2)=11 => DECODER_ERROR,
 //      Q(6)=1 &&
-//         Vd(0)=1 => UNDEFINED]}
+//         Vd(0)=1 => UNDEFINED],
+//    uses: {}}
 class Actual_VBIC_immediate_1111001i1d000mmmddddcccc0q11mmmm_case_1
      : public ClassDecoder {
  public:
   Actual_VBIC_immediate_1111001i1d000mmmddddcccc0q11mmmm_case_1()
      : ClassDecoder() {}
+  virtual RegisterList defs(Instruction inst) const;
   virtual SafetyLevel safety(Instruction i) const;
+  virtual RegisterList uses(Instruction i) const;
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(
       Actual_VBIC_immediate_1111001i1d000mmmddddcccc0q11mmmm_case_1);
 };
 
 // Actual_VCNT_111100111d11ss00dddd01010qm0mmmm_case_1
 //
 // Actual:
 //   {defs: {},
 //    safety: [inst(19:18)=~00 => UNDEFINED,
@@ skipping 3647 matching lines @@
   virtual SafetyLevel safety(Instruction i) const;
   virtual RegisterList uses(Instruction i) const;
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(
       Actual_VMOV_between_two_ARM_core_registers_and_two_single_precision_registers_cccc1100010otttttttt101000m1mmmm_case_1);
 };
 
 // Actual_VMOV_immediate_A1_1111001m1d000mmmddddcccc0qp1mmmm_case_1
 //
 // Actual:
-//   {safety: [inst(5)=0 &&
+//   {defs: {},
+//    safety: [inst(5)=0 &&
 //         inst(11:8)(0)=1 &&
 //         inst(11:8)(3:2)=~11 => DECODER_ERROR,
 //      inst(5)=1 &&
 //         inst(11:8)=~1110 => DECODER_ERROR,
 //      inst(6)=1 &&
-//         inst(15:12)(0)=1 => UNDEFINED]}
+//         inst(15:12)(0)=1 => UNDEFINED],
+//    uses: {}}
 //
 // Baseline:
 //   {D: D(22),
 //    Q: Q(6),
 //    Vd: Vd(15:12),
 //    arch: ASIMD,
 //    baseline: Vector1RegisterImmediate_MOV,
 //    cmode: cmode(11:8),
 //    constraints: ,
 //    d: D:Vd,
+//    defs: {},
 //    false: false,
 //    fields: [i(24),
 //      D(22),
 //      imm3(18:16),
 //      Vd(15:12),
 //      cmode(11:8),
 //      Q(6),
 //      op(5),
 //      imm4(3:0)],
 //    generated_baseline: VMOV_immediate_A1_1111001m1d000mmmddddcccc0qp1mmmm_case_0,
 //    i: i(24),
 //    imm3: imm3(18:16),
 //    imm4: imm4(3:0),
 //    imm64: AdvSIMDExpandImm(op, cmode, i:imm3:imm4),
 //    op: op(5),
 //    pattern: 1111001m1d000mmmddddcccc0qp1mmmm,
 //    regs: 1
 //         if Q(6)=0
 //         else 2,
 //    rule: VMOV_immediate_A1,
 //    safety: [op(5)=0 &&
 //         cmode(0)=1 &&
 //         cmode(3:2)=~11 => DECODER_ERROR,
 //      op(5)=1 &&
 //         cmode(11:8)=~1110 => DECODER_ERROR,
 //      Q(6)=1 &&
 //         Vd(0)=1 => UNDEFINED],
-//    single_register: false}
+//    single_register: false,
+//    uses: {}}
 class Actual_VMOV_immediate_A1_1111001m1d000mmmddddcccc0qp1mmmm_case_1
      : public ClassDecoder {
  public:
   Actual_VMOV_immediate_A1_1111001m1d000mmmddddcccc0qp1mmmm_case_1()
      : ClassDecoder() {}
+  virtual RegisterList defs(Instruction inst) const;
   virtual SafetyLevel safety(Instruction i) const;
+  virtual RegisterList uses(Instruction i) const;
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(
       Actual_VMOV_immediate_A1_1111001m1d000mmmddddcccc0qp1mmmm_case_1);
 };
 
 // Actual_VMRS_cccc111011110001tttt101000010000_case_1
 //
 // Actual:
 //   {defs: {16
 //         if 15  ==
@@ skipping 189 matching lines @@
   virtual SafetyLevel safety(Instruction i) const;
   virtual RegisterList uses(Instruction i) const;
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(
       Actual_VMUL_polynomial_A1_1111001u0dssnnnndddd1001nqm1mmmm_case_1);
 };
 
 // Actual_VMVN_immediate_1111001i1d000mmmddddcccc0q11mmmm_case_1
 //
 // Actual:
-//   {safety: [(inst(11:8)(0)=1 &&
+//   {defs: {},
+//    safety: [(inst(11:8)(0)=1 &&
 //         inst(11:8)(3:2)=~11) ||
 //         inst(11:8)(3:1)=111 => DECODER_ERROR,
 //      inst(6)=1 &&
-//         inst(15:12)(0)=1 => UNDEFINED]}
+//         inst(15:12)(0)=1 => UNDEFINED],
+//    uses: {}}
 //
 // Baseline:
 //   {D: D(22),
 //    Q: Q(6),
 //    Vd: Vd(15:12),
 //    arch: ASIMD,
 //    baseline: Vector1RegisterImmediate_MVN,
 //    cmode: cmode(11:8),
 //    constraints: ,
 //    d: D:Vd,
+//    defs: {},
 //    fields: [i(24),
 //      D(22),
 //      imm3(18:16),
 //      Vd(15:12),
 //      cmode(11:8),
 //      Q(6),
 //      op(5),
 //      imm4(3:0)],
 //    generated_baseline: VMVN_immediate_1111001i1d000mmmddddcccc0q11mmmm_case_0,
 //    i: i(24),
 //    imm3: imm3(18:16),
 //    imm4: imm4(3:0),
 //    imm64: AdvSIMDExpandImm(op, cmode, i:imm3:imm4),
 //    op: op(5),
 //    pattern: 1111001i1d000mmmddddcccc0q11mmmm,
 //    regs: 1
 //         if Q(6)=0
 //         else 2,
 //    rule: VMVN_immediate,
 //    safety: [(cmode(0)=1 &&
 //         cmode(3:2)=~11) ||
 //         cmode(3:1)=111 => DECODER_ERROR,
 //      Q(6)=1 &&
-//         Vd(0)=1 => UNDEFINED]}
+//         Vd(0)=1 => UNDEFINED],
+//    uses: {}}
 class Actual_VMVN_immediate_1111001i1d000mmmddddcccc0q11mmmm_case_1
      : public ClassDecoder {
  public:
   Actual_VMVN_immediate_1111001i1d000mmmddddcccc0q11mmmm_case_1()
      : ClassDecoder() {}
+  virtual RegisterList defs(Instruction inst) const;
   virtual SafetyLevel safety(Instruction i) const;
+  virtual RegisterList uses(Instruction i) const;
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(
       Actual_VMVN_immediate_1111001i1d000mmmddddcccc0q11mmmm_case_1);
 };
 
 // Actual_VPADD_floating_point_111100110d0snnnndddd1101nqm0mmmm_case_1
 //
 // Actual:
 //   {defs: {},
 //    safety: [inst(21:20)(0)=1 ||
@@ skipping 2522 matching lines @@
   virtual SafetyLevel safety(Instruction i) const;
   virtual RegisterList uses(Instruction i) const;
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(
       Actual_VUZP_111100111d11ss10dddd00010qm0mmmm_case_1);
 };
 
 } // namespace nacl_arm_test
 
 #endif  // NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_GEN_ARM32_DECODE_ACTUALS_2_H_