Add uses to two ARM tables.

src/trusted/validator_arm/armv7.table

 # ARMv7 Instruction Encodings
 #
 # This table is derived from the "ARM Architecture Reference Manual, ARMv7-A
 # and ARMv7-R edition" and is used here with the permission of ARM Limited.
 # Reproduction for purposes other than the development and distribution of
 # Native Client may require the explicit permission of ARM Limited.
 
 # This file defines the Native Client "instruction classes" assigned to every
 # possible ARMv7 instruction encoding.  It is organized into a series of tables,
 # and directly parallels the ARM Architecture Reference Manual cited above.
@@ skipping 3494 matching lines @@
                      rule := VRECPE;
 | "        10x1x   = *V2RM_IF32
                      pattern := 111100111d11ss11dddd010f1qm0mmmm;
                      rule := VRSQRTE;
 | "        11xxx   = *V2RM_CVT_F2I
                      pattern := 111100111d11ss11dddd011ppqm0mmmm;
                      rule := VCVT;
 | else:            = Undefined
 +--
 
-# TODO(karl): Add uses to corresponding classes.
 +-- simd_dp_1imm (See Section A7.4.6)
 *V1RI
    { i(24), D(22), imm3(18:16), Vd(15:12), cmode(11:8), Q(6), op(5), imm4(3:0) }
    baseline := Vector1RegisterImmediate;
    imm64 := AdvSIMDExpandImm(op, cmode, i:imm3:imm4);
    d := D:Vd; regs := 1 if Q=0 else 2;
+   # TODO(karl): Add vector defs/uses etc.
+   defs := {};
+   uses := {};
    arch := ASIMD;
 *V1RI_MOV *V1RI
    baseline := Vector1RegisterImmediate_MOV;
    single_register := false;
    safety := op=0 & cmode(0)=1 & cmode(3:2)=~11 => DECODER_ERROR &
              op=1 & cmode=~1110 => DECODER_ERROR &
              Q=1 & Vd(0)=1 => UNDEFINED;
 *V1RI_BIT *V1RI
    baseline := Vector1RegisterImmediate_BIT;
    safety := cmode(0)=0 | cmode(3:2)=11 => DECODER_ERROR &
@@ skipping 33 matching lines @@
                       rule := VBIC_immediate;
 | "     110x        = *V1RI_MVN
                       pattern := 1111001i1d000mmmddddcccc0q11mmmm;
                       rule := VMVN_immediate;
 | "     1110        = *V1RI_MOV
                       pattern := 1111001m1d000mmmddddcccc0qp1mmmm;
                       rule := VMOV_immediate_A1;
 | "     1111        = Undefined
 +--
 
-# TODO(karl): Add uses to corresponding classes.
 +-- advanced_simd_element_or_structure_load_store_instructions (See Section A7.7)
 *VLSM
    { D(22), Rn(19:16), Vd(15:12), type(11:8), size(7:6), align(5:4), Rm(3:0) }
    baseline := VectorLoadStoreMultiple;
    alignment := 1 if align=00 else 4 << align;
    ebytes := 1 << size; esize := 8 * ebytes; elements := 8 / ebytes;
    d := D:Vd; n := Rn; m := Rm;
    wback := (m != Pc); register_index := (m != Pc & m != Sp);
    base := n;
+   # TODO(karl): Add vector defs/uses etc.
    # defs ignores FPRs. It only models GPRs and conditions.
    defs := { base } if wback else {};
    # Note: register_index defines if Rm is used (rather than a small constant).
    small_imm_base_wb := not register_index;
    # uses ignores FPRs. It only models GPRs.
    uses := { m if wback else None , n };
    arch := ASIMD;
 *VLSM1 *VLSM
    baseline := VectorLoadStoreMultiple1;
    regs := 1 if type=0111 else
@@ skipping 38 matching lines @@
             index_align(3:2) if size=01 else
             index_align(3)   if size=10 else
             0;  # error value.
    inc := 1 if size=00 else
           (1 if index_align(1)=0 else 2) if size=01 else
           (1 if index_align(2)=0 else 2) if size=10 else
           0;  # error value.
    d := D:Vd; n := Rn; m := Rm;
    wback := (m != Pc); register_index := (m != Pc & m != Sp);
    base := n;
+   # TODO(karl): Add vector defs/uses etc.
    # defs ignores FPRs. It only models GPRs and conditions.
    defs := { base } if wback else {};
    # Note: register_index defines if Rm is used (rather than a small constant).
    small_imm_base_wb := not register_index;
    # uses ignores FPRs. It only models GPRs.
    uses := { m if wback else None , n };
    arch := ASIMD;
 *VLSS1 *VLSS
    baseline := VectorLoadStoreSingle1;
    alignment := 1 if size=00 else
@@ skipping 37 matching lines @@
    safety := size=11 => UNDEFINED &
              size=10 & index_align(1:0)=11 => UNDEFINED &
              n == Pc | d4 > 31 => UNPREDICTABLE;
 *VLSA
    { D(22), Rn(19:16), Vd(15:12), size(7:6), T(5), a(4), Rm(3:0) }
    baseline := VectorLoadSingleAllLanes;
    ebytes := 1 << size; elements := 8 / ebytes;
    d := D:Vd; n := Rn; m := Rm;
    wback := (m != Pc); register_index := (m != Pc & m != Sp);
    base := n;
+   # TODO(karl): Add vector defs/uses etc.
    # defs ignores FPRs. It only models GPRs and conditions.
    defs := { base } if wback else {};
    # Note: register_index defines if Rm is used (rather than a small constant).
    small_imm_base_wb := not register_index;
    # uses ignores FPRs. It only models GPRs.
    uses := { m if wback else None , n };
    arch := ASIMD;
 *VLS1A *VLSA
    baseline := VectorLoadSingle1AllLanes;
    alignment := 1 if a=0 else ebytes;
@@ skipping 94 matching lines @@
                     rule := VLD3_single_3_element_structure_to_all_lanes;
 | " "     0x11    = *VLSS4
                     pattern := 111101001d10nnnnddddss11aaaammmm;
                     rule := VLD4_single_4_element_structure_to_one_lane;
 | " "     1011    "
 | " "     1111    = *VLS4A
                     pattern := 111101001d10nnnndddd1111sstammmm;
                     rule := VLD4_single_4_element_structure_to_all_lanes;
 | else:           = Undefined
 +--