Index: src/mips/assembler-mips.cc |
diff --git a/src/mips/assembler-mips.cc b/src/mips/assembler-mips.cc |
index 22f1e1b866d87de0b2a3d0b36150c41e086c4c7b..1ca4d525da82fd715cf4fb76e2603cdbc8fd3c54 100644 |
--- a/src/mips/assembler-mips.cc |
+++ b/src/mips/assembler-mips.cc |
@@ -876,6 +876,20 @@ void Assembler::GenInstrRegister(Opcode opcode, |
void Assembler::GenInstrRegister(Opcode opcode, |
+ FPURegister fr, |
+ FPURegister ft, |
+ FPURegister fs, |
+ FPURegister fd, |
+ SecondaryField func) { |
+ ASSERT(fd.is_valid() && fr.is_valid() && fs.is_valid() && ft.is_valid()); |
+ ASSERT(CpuFeatures::IsEnabled(FPU)); |
+ Instr instr = opcode | (fr.code() << kFrShift) | (ft.code() << kFtShift) |
+ | (fs.code() << kFsShift) | (fd.code() << kFdShift) | func; |
+ emit(instr); |
+} |
+ |
+ |
+void Assembler::GenInstrRegister(Opcode opcode, |
SecondaryField fmt, |
Register rt, |
FPURegister fs, |
@@ -1680,6 +1694,12 @@ void Assembler::mul_d(FPURegister fd, FPURegister fs, FPURegister ft) { |
} |
+void Assembler::madd_d(FPURegister fd, FPURegister fr, FPURegister fs, |
+ FPURegister ft) { |
+ GenInstrRegister(COP1X, fr, ft, fs, fd, MADD_D); |
+} |
+ |
+ |
void Assembler::div_d(FPURegister fd, FPURegister fs, FPURegister ft) { |
GenInstrRegister(COP1, D, ft, fs, fd, DIV_D); |
} |