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| 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
| 2 // All Rights Reserved. | 2 // All Rights Reserved. |
| 3 // | 3 // |
| 4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
| 5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
| 6 // are met: | 6 // are met: |
| 7 // | 7 // |
| 8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
| 9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
| 10 // | 10 // |
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| 248 patcher.masm()->int3(); | 248 patcher.masm()->int3(); |
| 249 } | 249 } |
| 250 } | 250 } |
| 251 | 251 |
| 252 | 252 |
| 253 // ----------------------------------------------------------------------------- | 253 // ----------------------------------------------------------------------------- |
| 254 // Implementation of Operand | 254 // Implementation of Operand |
| 255 | 255 |
| 256 Operand::Operand(Register base, int32_t disp, RelocInfo::Mode rmode) { | 256 Operand::Operand(Register base, int32_t disp, RelocInfo::Mode rmode) { |
| 257 // [base + disp/r] | 257 // [base + disp/r] |
| 258 if (disp == 0 && rmode == RelocInfo::NONE32 && !base.is(ebp)) { | 258 if (disp == 0 && RelocInfo::IsNone(rmode) && !base.is(ebp)) { |
| 259 // [base] | 259 // [base] |
| 260 set_modrm(0, base); | 260 set_modrm(0, base); |
| 261 if (base.is(esp)) set_sib(times_1, esp, base); | 261 if (base.is(esp)) set_sib(times_1, esp, base); |
| 262 } else if (is_int8(disp) && rmode == RelocInfo::NONE32) { | 262 } else if (is_int8(disp) && RelocInfo::IsNone(rmode)) { |
| 263 // [base + disp8] | 263 // [base + disp8] |
| 264 set_modrm(1, base); | 264 set_modrm(1, base); |
| 265 if (base.is(esp)) set_sib(times_1, esp, base); | 265 if (base.is(esp)) set_sib(times_1, esp, base); |
| 266 set_disp8(disp); | 266 set_disp8(disp); |
| 267 } else { | 267 } else { |
| 268 // [base + disp/r] | 268 // [base + disp/r] |
| 269 set_modrm(2, base); | 269 set_modrm(2, base); |
| 270 if (base.is(esp)) set_sib(times_1, esp, base); | 270 if (base.is(esp)) set_sib(times_1, esp, base); |
| 271 set_dispr(disp, rmode); | 271 set_dispr(disp, rmode); |
| 272 } | 272 } |
| 273 } | 273 } |
| 274 | 274 |
| 275 | 275 |
| 276 Operand::Operand(Register base, | 276 Operand::Operand(Register base, |
| 277 Register index, | 277 Register index, |
| 278 ScaleFactor scale, | 278 ScaleFactor scale, |
| 279 int32_t disp, | 279 int32_t disp, |
| 280 RelocInfo::Mode rmode) { | 280 RelocInfo::Mode rmode) { |
| 281 ASSERT(!index.is(esp)); // illegal addressing mode | 281 ASSERT(!index.is(esp)); // illegal addressing mode |
| 282 // [base + index*scale + disp/r] | 282 // [base + index*scale + disp/r] |
| 283 if (disp == 0 && rmode == RelocInfo::NONE32 && !base.is(ebp)) { | 283 if (disp == 0 && RelocInfo::IsNone(rmode) && !base.is(ebp)) { |
| 284 // [base + index*scale] | 284 // [base + index*scale] |
| 285 set_modrm(0, esp); | 285 set_modrm(0, esp); |
| 286 set_sib(scale, index, base); | 286 set_sib(scale, index, base); |
| 287 } else if (is_int8(disp) && rmode == RelocInfo::NONE32) { | 287 } else if (is_int8(disp) && RelocInfo::IsNone(rmode)) { |
| 288 // [base + index*scale + disp8] | 288 // [base + index*scale + disp8] |
| 289 set_modrm(1, esp); | 289 set_modrm(1, esp); |
| 290 set_sib(scale, index, base); | 290 set_sib(scale, index, base); |
| 291 set_disp8(disp); | 291 set_disp8(disp); |
| 292 } else { | 292 } else { |
| 293 // [base + index*scale + disp/r] | 293 // [base + index*scale + disp/r] |
| 294 set_modrm(2, esp); | 294 set_modrm(2, esp); |
| 295 set_sib(scale, index, base); | 295 set_sib(scale, index, base); |
| 296 set_dispr(disp, rmode); | 296 set_dispr(disp, rmode); |
| 297 } | 297 } |
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| 1173 EnsureSpace ensure_space(this); | 1173 EnsureSpace ensure_space(this); |
| 1174 EMIT(0x29); | 1174 EMIT(0x29); |
| 1175 emit_operand(src, dst); | 1175 emit_operand(src, dst); |
| 1176 } | 1176 } |
| 1177 | 1177 |
| 1178 | 1178 |
| 1179 void Assembler::test(Register reg, const Immediate& imm) { | 1179 void Assembler::test(Register reg, const Immediate& imm) { |
| 1180 EnsureSpace ensure_space(this); | 1180 EnsureSpace ensure_space(this); |
| 1181 // Only use test against byte for registers that have a byte | 1181 // Only use test against byte for registers that have a byte |
| 1182 // variant: eax, ebx, ecx, and edx. | 1182 // variant: eax, ebx, ecx, and edx. |
| 1183 if (imm.rmode_ == RelocInfo::NONE32 && | 1183 if (RelocInfo::IsNone(imm.rmode_) && |
| 1184 is_uint8(imm.x_) && | 1184 is_uint8(imm.x_) && |
| 1185 reg.is_byte_register()) { | 1185 reg.is_byte_register()) { |
| 1186 uint8_t imm8 = imm.x_; | 1186 uint8_t imm8 = imm.x_; |
| 1187 if (reg.is(eax)) { | 1187 if (reg.is(eax)) { |
| 1188 EMIT(0xA8); | 1188 EMIT(0xA8); |
| 1189 EMIT(imm8); | 1189 EMIT(imm8); |
| 1190 } else { | 1190 } else { |
| 1191 emit_arith_b(0xF6, 0xC0, reg, imm8); | 1191 emit_arith_b(0xF6, 0xC0, reg, imm8); |
| 1192 } | 1192 } |
| 1193 } else { | 1193 } else { |
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| 2607 ASSERT(length > 0); | 2607 ASSERT(length > 0); |
| 2608 | 2608 |
| 2609 // Emit updated ModRM byte containing the given register. | 2609 // Emit updated ModRM byte containing the given register. |
| 2610 pc_[0] = (adr.buf_[0] & ~0x38) | (reg.code() << 3); | 2610 pc_[0] = (adr.buf_[0] & ~0x38) | (reg.code() << 3); |
| 2611 | 2611 |
| 2612 // Emit the rest of the encoded operand. | 2612 // Emit the rest of the encoded operand. |
| 2613 for (unsigned i = 1; i < length; i++) pc_[i] = adr.buf_[i]; | 2613 for (unsigned i = 1; i < length; i++) pc_[i] = adr.buf_[i]; |
| 2614 pc_ += length; | 2614 pc_ += length; |
| 2615 | 2615 |
| 2616 // Emit relocation information if necessary. | 2616 // Emit relocation information if necessary. |
| 2617 if (length >= sizeof(int32_t) && adr.rmode_ != RelocInfo::NONE32) { | 2617 if (length >= sizeof(int32_t) && !RelocInfo::IsNone(adr.rmode_)) { |
| 2618 pc_ -= sizeof(int32_t); // pc_ must be *at* disp32 | 2618 pc_ -= sizeof(int32_t); // pc_ must be *at* disp32 |
| 2619 RecordRelocInfo(adr.rmode_); | 2619 RecordRelocInfo(adr.rmode_); |
| 2620 pc_ += sizeof(int32_t); | 2620 pc_ += sizeof(int32_t); |
| 2621 } | 2621 } |
| 2622 } | 2622 } |
| 2623 | 2623 |
| 2624 | 2624 |
| 2625 void Assembler::emit_farith(int b1, int b2, int i) { | 2625 void Assembler::emit_farith(int b1, int b2, int i) { |
| 2626 ASSERT(is_uint8(b1) && is_uint8(b2)); // wrong opcode | 2626 ASSERT(is_uint8(b1) && is_uint8(b2)); // wrong opcode |
| 2627 ASSERT(0 <= i && i < 8); // illegal stack offset | 2627 ASSERT(0 <= i && i < 8); // illegal stack offset |
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| 2681 fprintf(coverage_log, "%s\n", file_line); | 2681 fprintf(coverage_log, "%s\n", file_line); |
| 2682 fflush(coverage_log); | 2682 fflush(coverage_log); |
| 2683 } | 2683 } |
| 2684 } | 2684 } |
| 2685 | 2685 |
| 2686 #endif | 2686 #endif |
| 2687 | 2687 |
| 2688 } } // namespace v8::internal | 2688 } } // namespace v8::internal |
| 2689 | 2689 |
| 2690 #endif // V8_TARGET_ARCH_IA32 | 2690 #endif // V8_TARGET_ARCH_IA32 |
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