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1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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1696 | 1696 |
1697 bool CompareIC::HasInlinedSmiCode(Address address) { | 1697 bool CompareIC::HasInlinedSmiCode(Address address) { |
1698 // The address of the instruction following the call. | 1698 // The address of the instruction following the call. |
1699 Address andi_instruction_address = | 1699 Address andi_instruction_address = |
1700 address + Assembler::kCallTargetAddressOffset; | 1700 address + Assembler::kCallTargetAddressOffset; |
1701 | 1701 |
1702 // If the instruction following the call is not a andi at, rx, #yyy, nothing | 1702 // If the instruction following the call is not a andi at, rx, #yyy, nothing |
1703 // was inlined. | 1703 // was inlined. |
1704 Instr instr = Assembler::instr_at(andi_instruction_address); | 1704 Instr instr = Assembler::instr_at(andi_instruction_address); |
1705 return Assembler::IsAndImmediate(instr) && | 1705 return Assembler::IsAndImmediate(instr) && |
1706 Assembler::GetRt(instr) == (uint32_t)zero_reg.code(); | 1706 Assembler::GetRt(instr) == static_cast<uint32_t>(zero_reg.code()); |
1707 } | 1707 } |
1708 | 1708 |
1709 | 1709 |
1710 void PatchInlinedSmiCode(Address address, InlinedSmiCheck check) { | 1710 void PatchInlinedSmiCode(Address address, InlinedSmiCheck check) { |
1711 Address andi_instruction_address = | 1711 Address andi_instruction_address = |
1712 address + Assembler::kCallTargetAddressOffset; | 1712 address + Assembler::kCallTargetAddressOffset; |
1713 | 1713 |
1714 // If the instruction following the call is not a andi at, rx, #yyy, nothing | 1714 // If the instruction following the call is not a andi at, rx, #yyy, nothing |
1715 // was inlined. | 1715 // was inlined. |
1716 Instr instr = Assembler::instr_at(andi_instruction_address); | 1716 Instr instr = Assembler::instr_at(andi_instruction_address); |
1717 if (!(Assembler::IsAndImmediate(instr) && | 1717 if (!(Assembler::IsAndImmediate(instr) && |
1718 Assembler::GetRt(instr) == (uint32_t)zero_reg.code())) { | 1718 Assembler::GetRt(instr) == static_cast<uint32_t>(zero_reg.code()))) { |
1719 return; | 1719 return; |
1720 } | 1720 } |
1721 | 1721 |
1722 // The delta to the start of the map check instruction and the | 1722 // The delta to the start of the map check instruction and the |
1723 // condition code uses at the patched jump. | 1723 // condition code uses at the patched jump. |
1724 int delta = Assembler::GetImmediate16(instr); | 1724 int delta = Assembler::GetImmediate16(instr); |
1725 delta += Assembler::GetRs(instr) * kImm16Mask; | 1725 delta += Assembler::GetRs(instr) * kImm16Mask; |
1726 // If the delta is 0 the instruction is andi at, zero_reg, #0 which also | 1726 // If the delta is 0 the instruction is andi at, zero_reg, #0 which also |
1727 // signals that nothing was inlined. | 1727 // signals that nothing was inlined. |
1728 if (delta == 0) { | 1728 if (delta == 0) { |
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1766 } else { | 1766 } else { |
1767 ASSERT(Assembler::IsBne(branch_instr)); | 1767 ASSERT(Assembler::IsBne(branch_instr)); |
1768 patcher.ChangeBranchCondition(eq); | 1768 patcher.ChangeBranchCondition(eq); |
1769 } | 1769 } |
1770 } | 1770 } |
1771 | 1771 |
1772 | 1772 |
1773 } } // namespace v8::internal | 1773 } } // namespace v8::internal |
1774 | 1774 |
1775 #endif // V8_TARGET_ARCH_MIPS | 1775 #endif // V8_TARGET_ARCH_MIPS |
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