Fix uses in ARM table media_instructions.

src/trusted/validator_arm/gen/arm32_decode.cc

 /*
  * Copyright 2012 The Native Client Authors.  All rights reserved.
  * Use of this source code is governed by a BSD-style license that can
  * be found in the LICENSE file.
  */
 
 // DO NOT EDIT: GENERATED CODE
 
 
 #include "native_client/src/trusted/validator_arm/gen/arm32_decode.h"
 
 namespace nacl_arm_dec {
 
 
 Arm32DecoderState::Arm32DecoderState() : DecoderState()
+  , Binary2RegisterBitRangeMsbGeLsb_instance_()
+  , Binary2RegisterBitRangeNotRnIsPcBitfieldExtract_instance_()
   , Binary2RegisterImmedShiftedTest_instance_()
   , Binary2RegisterImmediateOp_instance_()
   , Binary2RegisterImmediateOpAddSub_instance_()
   , Binary2RegisterImmediateOpDynCodeReplace_instance_()
   , Binary3RegisterOp_instance_()
   , Binary3RegisterOpAltA_instance_()
   , Binary3RegisterOpAltANoCondsUpdate_instance_()
   , Binary3RegisterOpAltBNoCondUpdates_instance_()
   , Binary3RegisterShiftedOp_instance_()
   , Binary3RegisterShiftedTest_instance_()
   , Binary4RegisterDualOp_instance_()
   , Binary4RegisterDualOpLtV6RdNotRn_instance_()
   , Binary4RegisterDualOpNoCondsUpdate_instance_()
   , Binary4RegisterDualResult_instance_()
   , Binary4RegisterDualResultLtV6RdHiLoNotRn_instance_()
   , Binary4RegisterDualResultNoCondsUpdate_instance_()
   , Binary4RegisterDualResultUsesRnRm_instance_()
   , Binary4RegisterShiftedOp_instance_()
   , BinaryRegisterImmediateTest_instance_()
   , Branch_instance_()
   , BranchToRegister_instance_()
   , BreakPointAndConstantPoolHead_instance_()
   , DataBarrier_instance_()
-  , Defs12To15CondsDontCareMsbGeLsb_instance_()
   , Defs12To15CondsDontCareRdRnNotPc_instance_()
-  , Defs12To15CondsDontCareRdRnNotPcBitfieldExtract_instance_()
   , Defs12To15CondsDontCareRnRdRmNotPc_instance_()
-  , Defs16To19CondsDontCareRdRaRmRnNotPc_instance_()
-  , Defs16To19CondsDontCareRdRmRnNotPc_instance_()
   , Deprecated_instance_()
   , DontCareInst_instance_()
   , DontCareInstRdNotPc_instance_()
   , DuplicateToAdvSIMDRegisters_instance_()
   , Forbidden_instance_()
   , ForbiddenCondDecoder_instance_()
   , InstructionBarrier_instance_()
   , LdrImmediateOp_instance_()
   , Load2RegisterImm12Op_instance_()
   , Load2RegisterImm8DoubleOp_instance_()
@@ skipping 982 matching lines @@
 }
 
 // Implementation of table: media_instructions.
 // Specified by: See Section A5.4
 const ClassDecoder& Arm32DecoderState::decode_media_instructions(
      const Instruction inst) const
 {
   if ((inst.Bits() & 0x01F00000) == 0x01800000 /* op1(24:20)=11000 */ &&
       (inst.Bits() & 0x000000E0) == 0x00000000 /* op2(7:5)=000 */ &&
       (inst.Bits() & 0x0000F000) != 0x0000F000 /* Rd(15:12)=~1111 */) {
-    return Defs16To19CondsDontCareRdRaRmRnNotPc_instance_;
+    return Binary4RegisterDualOp_instance_;
   }
 
   if ((inst.Bits() & 0x01F00000) == 0x01800000 /* op1(24:20)=11000 */ &&
       (inst.Bits() & 0x000000E0) == 0x00000000 /* op2(7:5)=000 */ &&
       (inst.Bits() & 0x0000F000) == 0x0000F000 /* Rd(15:12)=1111 */) {
-    return Defs16To19CondsDontCareRdRmRnNotPc_instance_;
+    return Binary3RegisterOpAltA_instance_;
   }
 
   if ((inst.Bits() & 0x01F00000) == 0x01F00000 /* op1(24:20)=11111 */ &&
       (inst.Bits() & 0x000000E0) == 0x000000E0 /* op2(7:5)=111 */) {
     return PermanentlyUndefined_instance_;
   }
 
   if ((inst.Bits() & 0x01E00000) == 0x01C00000 /* op1(24:20)=1110x */ &&
       (inst.Bits() & 0x00000060) == 0x00000000 /* op2(7:5)=x00 */ &&
       (inst.Bits() & 0x0000000F) != 0x0000000F /* Rn(3:0)=~1111 */) {
-    return Defs12To15CondsDontCareMsbGeLsb_instance_;
+    return Binary2RegisterBitRangeMsbGeLsb_instance_;
   }
 
   if ((inst.Bits() & 0x01E00000) == 0x01C00000 /* op1(24:20)=1110x */ &&
       (inst.Bits() & 0x00000060) == 0x00000000 /* op2(7:5)=x00 */ &&
       (inst.Bits() & 0x0000000F) == 0x0000000F /* Rn(3:0)=1111 */) {
     return Unary1RegisterBitRangeMsbGeLsb_instance_;
   }
 
   if ((inst.Bits() & 0x01A00000) == 0x01A00000 /* op1(24:20)=11x1x */ &&
       (inst.Bits() & 0x00000060) == 0x00000040 /* op2(7:5)=x10 */) {
-    return Defs12To15CondsDontCareRdRnNotPcBitfieldExtract_instance_;
+    return Binary2RegisterBitRangeNotRnIsPcBitfieldExtract_instance_;
   }
 
   if ((inst.Bits() & 0x01C00000) == 0x00000000 /* op1(24:20)=000xx */) {
     return decode_parallel_addition_and_subtraction_signed(inst);
   }
 
   if ((inst.Bits() & 0x01C00000) == 0x00400000 /* op1(24:20)=001xx */) {
     return decode_parallel_addition_and_subtraction_unsigned(inst);
   }
 
@@ skipping 1313 matching lines @@
 
   // Catch any attempt to fall though ...
   return not_implemented_;
 }
 
 const ClassDecoder& Arm32DecoderState::decode(const Instruction inst) const {
   return decode_ARMv7(inst);
 }
 
 }  // namespace nacl_arm_dec