Fix uses in ARM table media_instructions.

src/trusted/validator_arm/baseline_classes.h

 /*
  * Copyright (c) 2012 The Native Client Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #ifndef NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_BASELINE_CLASSES_H_
 #define NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_BASELINE_CLASSES_H_
 
 #include "native_client/src/trusted/validator_arm/inst_classes.h"
@@ skipping 423 matching lines @@
 
   Unary1RegisterImmediateOpPc() {}
   virtual SafetyLevel safety(Instruction i) const;
   virtual RegisterList defs(Instruction i) const;
   virtual RegisterList uses(Instruction i) const;
 
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(Unary1RegisterImmediateOpPc);
 };
 
+// Models a 1-register unary operation with two immediate 5 values
+// defining a bit range.
+// Op<c> Rd, #lsb, #width
+// +--------+--------------+----------+--------+----------+--------------+
+// |31302928|27262524232221|2019181716|15141312|1110 9 8 7| 6 5 4 3 2 1 0|
+// +--------+--------------+----------+--------+----------+--------------+
+// |  cond  |              |    msb   |   Rd   |   lsb    |              |
+// +--------+--------------+----------+--------+----------+--------------+
+// Definitions
+//    Rd = The destination register.
+//    lsb = The least significant bit to be modified.
+//    msb = lsb + width - 1 - The most significant bit to be modified
+//    width = msb - lsb + 1 - The number of bits to be modified.
+//
+// If Rd is R15 or msbit < lsbit, the instruction is unpredictable.
+// NaCl disallows writing to PC to cause a jump.
+// Note: Currently, only implements bfc.
+class Unary1RegisterBitRangeMsbGeLsb : public ClassDecoder {
+ public:
+  // Interface for components of the instruction.
+  static const Imm5Bits7To11Interface lsb;
+  static const RegBits12To15Interface d;
+  static const Imm5Bits16To20Interface msb;
+  static const ConditionBits28To31Interface cond;
+
+  // Methods for class.
+  Unary1RegisterBitRangeMsbGeLsb() : ClassDecoder() {}
+  virtual SafetyLevel safety(Instruction i) const;
+  virtual RegisterList defs(Instruction i) const;
+  virtual RegisterList uses(Instruction i) const;
+
+ private:
+  NACL_DISALLOW_COPY_AND_ASSIGN(Unary1RegisterBitRangeMsbGeLsb);
+};
+
 // Models a 2-register binary operation with two immediate values
 // defining a bit range.
 // Op<c> Rd, Rn, #<lsb>, #width
 // +--------+--------------+----------+--------+----------+------+--------+
 // |31302928|27262524232221|2019181716|15141312|1110 9 8 7| 6 5 4| 3 2 1 0|
 // +--------+--------------+----------+--------+----------+------+--------+
 // |  cond  |              |    msb   |   Rd   |    lsb   |      |   Rn   |
 // +--------+--------------+----------+--------+----------+------+--------+
 // Definitions:
 //   Rd = The destination register.
@@ skipping 10 matching lines @@
   static const RegBits0To3Interface n;
   static const Imm5Bits7To11Interface lsb;
   static const RegBits12To15Interface d;
   static const Imm5Bits16To20Interface msb;
   static const ConditionBits28To31Interface cond;
 
   // Methods for class.
   Binary2RegisterBitRangeMsbGeLsb() {}
   virtual SafetyLevel safety(Instruction i) const;
   virtual RegisterList defs(Instruction i) const;
+  virtual RegisterList uses(Instruction i) const;
 
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(Binary2RegisterBitRangeMsbGeLsb);
 };
 
 // Models a 2-register binary operation with two immediate values
 // defining a bit range.
 // Op<c> Rd, Rn, #<lsb>, #width
 // +--------+--------------+----------+--------+----------+------+--------+
 // |31302928|27262524232221|2019181716|15141312|1110 9 8 7| 6 5 4| 3 2 1 0|
@@ skipping 17 matching lines @@
   static const RegBits0To3Interface n;
   static const Imm5Bits7To11Interface lsb;
   static const RegBits12To15Interface d;
   static const Imm5Bits16To20Interface widthm1;
   static const ConditionBits28To31Interface cond;
 
   // Methods for class.
   Binary2RegisterBitRangeNotRnIsPcBitfieldExtract() {}
   virtual SafetyLevel safety(Instruction i) const;
   virtual RegisterList defs(Instruction i) const;
+  virtual RegisterList uses(Instruction i) const;
 
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(
       Binary2RegisterBitRangeNotRnIsPcBitfieldExtract);
 };
 
 // Models a 2-register binary operation with an immediate value.
 // Op(S)<c> <Rd>, <Rn>, #<const>
 // +--------+--------------+--+--------+--------+------------------------+
 // |31302928|27262524232221|20|19181716|15141312|1110 9 8 7 6 5 4 3 2 1 0|
@@ skipping 3143 matching lines @@
   InstructionBarrier() {}
   virtual SafetyLevel safety(Instruction i) const;
 
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(InstructionBarrier);
 };
 
 }  // namespace nacl_arm_dec
 
 #endif  // NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_BASELINE_CLASSES_H_