Fix uses in ARM table media_instructions.

src/trusted/validator_arm/baseline_classes.cc

 /*
  * Copyright (c) 2012 The Native Client Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "native_client/src/trusted/validator_arm/baseline_classes.h"
 
 #include <assert.h>
 #include <string.h>
@@ skipping 170 matching lines @@
 
 RegisterList Unary1RegisterImmediateOpPc::defs(Instruction i) const {
   return RegisterList(d.reg(i));
 }
 
 RegisterList Unary1RegisterImmediateOpPc::uses(Instruction i) const {
   UNREFERENCED_PARAMETER(i);
   return RegisterList(Register::Pc());
 }
 
+// Unary1RegisterBitRangeMsbGeLsb
+SafetyLevel Unary1RegisterBitRangeMsbGeLsb::safety(Instruction i) const {
+  if (d.reg(i).Equals(Register::Pc()) ||
+      msb.value(i) < lsb.value(i))
+    return UNPREDICTABLE;
+
+  // Note: We would restrict out PC as well for Rd in NaCl, but no need
+  // since the ARM restriction doesn't allow it anyway.
+  return MAY_BE_SAFE;
+}
+
+RegisterList Unary1RegisterBitRangeMsbGeLsb::defs(Instruction i) const {
+  return RegisterList(d.reg(i));
+}
+
+RegisterList Unary1RegisterBitRangeMsbGeLsb::uses(Instruction i) const {
+  return RegisterList(d.reg(i));
+}
+
 // Binary2RegisterBitRangeMsbGeLsb
 SafetyLevel Binary2RegisterBitRangeMsbGeLsb::safety(Instruction i) const {
   return (d.reg(i).Equals(Register::Pc()) ||
           (msb.value(i) < lsb.value(i)))
       ? UNPREDICTABLE
       : MAY_BE_SAFE;
 }
 
 RegisterList Binary2RegisterBitRangeMsbGeLsb::defs(Instruction i) const {
   return RegisterList(d.reg(i));
 }
 
+RegisterList Binary2RegisterBitRangeMsbGeLsb::uses(Instruction i) const {
+  return RegisterList(n.reg(i)).Add(d.reg(i));
+}
+
 // Binary2RegisterBitRangeNotRnIsPcBitfieldExtract
 SafetyLevel Binary2RegisterBitRangeNotRnIsPcBitfieldExtract
 ::safety(Instruction i) const {
   return (RegisterList(d.reg(i)).Add(n.reg(i)).Contains(Register::Pc()) ||
           (lsb.value(i) + widthm1.value(i) > 31))
       ? UNPREDICTABLE
       : MAY_BE_SAFE;
 }
 
 RegisterList Binary2RegisterBitRangeNotRnIsPcBitfieldExtract
 ::defs(Instruction i) const {
   return RegisterList(d.reg(i));
 }
 
+RegisterList Binary2RegisterBitRangeNotRnIsPcBitfieldExtract
+::uses(Instruction i) const {
+  return RegisterList(n.reg(i));
+}
+
 // Binary2RegisterImmediateOp
 SafetyLevel Binary2RegisterImmediateOp::safety(Instruction i) const {
   if (d.reg(i).Equals(Register::Pc())) {
     if (conditions.is_updated(i)) return DECODER_ERROR;
     // NaCl Constraint.
     return FORBIDDEN_OPERANDS;
   }
   return MAY_BE_SAFE;
 }
 
@@ skipping 113 matching lines @@
 }
 
 // Binary3RegisterOpAltA
 SafetyLevel Binary3RegisterOpAltA::safety(Instruction i) const {
   // Unsafe if any register contains PC (ARM restriction).
   if (RegisterList(d.reg(i)).Add(m.reg(i)).Add(n.reg(i)).
       Contains(Register::Pc())) {
     return UNPREDICTABLE;
   }
 
+  // TODO(karl): This doesn't apply to all uses in rows in armv7.table.
+  // However, it doesn't really matter since we only accept version 7.
   if ((ArchVersion() < 6) && m.reg(i).Equals(n.reg(i))) return UNPREDICTABLE;
 
   // Note: We would restrict out PC as well for Rd in NaCl, but no need
   // since the ARM restriction doesn't allow it anyway.
   return MAY_BE_SAFE;
 }
 
 RegisterList Binary3RegisterOpAltA::defs(Instruction i) const {
   return RegisterList(d.reg(i)).Add(conditions.conds_if_updated(i));
 }
@@ skipping 1770 matching lines @@
 }
 
 // InstructionBarrier
 SafetyLevel InstructionBarrier::safety(Instruction i) const {
   if (option.value(i) != 0xF)
     return FORBIDDEN_OPERANDS;
   return UncondDecoder::safety(i);
 }
 
 }  // namespace nacl_arm_dec