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1 /* | 1 /* |
2 * Copyright (c) 2012 The Native Client Authors. All rights reserved. | 2 * Copyright (c) 2012 The Native Client Authors. All rights reserved. |
3 * Use of this source code is governed by a BSD-style license that can be | 3 * Use of this source code is governed by a BSD-style license that can be |
4 * found in the LICENSE file. | 4 * found in the LICENSE file. |
5 */ | 5 */ |
6 | 6 |
7 #include "native_client/src/trusted/validator_arm/baseline_classes.h" | 7 #include "native_client/src/trusted/validator_arm/baseline_classes.h" |
8 | 8 |
9 #include <assert.h> | 9 #include <assert.h> |
10 #include <string.h> | 10 #include <string.h> |
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193 return (d.reg(i).Equals(Register::Pc()) || | 193 return (d.reg(i).Equals(Register::Pc()) || |
194 (msb.value(i) < lsb.value(i))) | 194 (msb.value(i) < lsb.value(i))) |
195 ? UNPREDICTABLE | 195 ? UNPREDICTABLE |
196 : MAY_BE_SAFE; | 196 : MAY_BE_SAFE; |
197 } | 197 } |
198 | 198 |
199 RegisterList Binary2RegisterBitRangeMsbGeLsb::defs(Instruction i) const { | 199 RegisterList Binary2RegisterBitRangeMsbGeLsb::defs(Instruction i) const { |
200 return RegisterList(d.reg(i)); | 200 return RegisterList(d.reg(i)); |
201 } | 201 } |
202 | 202 |
203 RegisterList Binary2RegisterBitRangeMsbGeLsb::uses(Instruction i) const { | |
204 return RegisterList(n.reg(i)); | |
JF
2012/12/14 22:39:33
And d.
Karl
2012/12/17 17:35:57
Done.
| |
205 } | |
206 | |
203 // Binary2RegisterBitRangeNotRnIsPcBitfieldExtract | 207 // Binary2RegisterBitRangeNotRnIsPcBitfieldExtract |
204 SafetyLevel Binary2RegisterBitRangeNotRnIsPcBitfieldExtract | 208 SafetyLevel Binary2RegisterBitRangeNotRnIsPcBitfieldExtract |
205 ::safety(Instruction i) const { | 209 ::safety(Instruction i) const { |
206 return (RegisterList(d.reg(i)).Add(n.reg(i)).Contains(Register::Pc()) || | 210 return (RegisterList(d.reg(i)).Add(n.reg(i)).Contains(Register::Pc()) || |
207 (lsb.value(i) + widthm1.value(i) > 31)) | 211 (lsb.value(i) + widthm1.value(i) > 31)) |
208 ? UNPREDICTABLE | 212 ? UNPREDICTABLE |
209 : MAY_BE_SAFE; | 213 : MAY_BE_SAFE; |
210 } | 214 } |
211 | 215 |
212 RegisterList Binary2RegisterBitRangeNotRnIsPcBitfieldExtract | 216 RegisterList Binary2RegisterBitRangeNotRnIsPcBitfieldExtract |
213 ::defs(Instruction i) const { | 217 ::defs(Instruction i) const { |
214 return RegisterList(d.reg(i)); | 218 return RegisterList(d.reg(i)); |
215 } | 219 } |
JF
2012/12/14 22:39:33
Add uses.
Karl
2012/12/17 17:35:57
Done.
| |
216 | 220 |
217 // Binary2RegisterImmediateOp | 221 // Binary2RegisterImmediateOp |
218 SafetyLevel Binary2RegisterImmediateOp::safety(Instruction i) const { | 222 SafetyLevel Binary2RegisterImmediateOp::safety(Instruction i) const { |
219 if (d.reg(i).Equals(Register::Pc())) { | 223 if (d.reg(i).Equals(Register::Pc())) { |
220 if (conditions.is_updated(i)) return DECODER_ERROR; | 224 if (conditions.is_updated(i)) return DECODER_ERROR; |
221 // NaCl Constraint. | 225 // NaCl Constraint. |
222 return FORBIDDEN_OPERANDS; | 226 return FORBIDDEN_OPERANDS; |
223 } | 227 } |
224 return MAY_BE_SAFE; | 228 return MAY_BE_SAFE; |
225 } | 229 } |
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340 } | 344 } |
341 | 345 |
342 // Binary3RegisterOpAltA | 346 // Binary3RegisterOpAltA |
343 SafetyLevel Binary3RegisterOpAltA::safety(Instruction i) const { | 347 SafetyLevel Binary3RegisterOpAltA::safety(Instruction i) const { |
344 // Unsafe if any register contains PC (ARM restriction). | 348 // Unsafe if any register contains PC (ARM restriction). |
345 if (RegisterList(d.reg(i)).Add(m.reg(i)).Add(n.reg(i)). | 349 if (RegisterList(d.reg(i)).Add(m.reg(i)).Add(n.reg(i)). |
346 Contains(Register::Pc())) { | 350 Contains(Register::Pc())) { |
347 return UNPREDICTABLE; | 351 return UNPREDICTABLE; |
348 } | 352 } |
349 | 353 |
354 // TODO(karl): This doesn't apply to all uses in rows in armv7.table. | |
355 // However, it doesn't really matter since we only accept version 7. | |
350 if ((ArchVersion() < 6) && m.reg(i).Equals(n.reg(i))) return UNPREDICTABLE; | 356 if ((ArchVersion() < 6) && m.reg(i).Equals(n.reg(i))) return UNPREDICTABLE; |
351 | 357 |
352 // Note: We would restrict out PC as well for Rd in NaCl, but no need | 358 // Note: We would restrict out PC as well for Rd in NaCl, but no need |
353 // since the ARM restriction doesn't allow it anyway. | 359 // since the ARM restriction doesn't allow it anyway. |
354 return MAY_BE_SAFE; | 360 return MAY_BE_SAFE; |
355 } | 361 } |
356 | 362 |
357 RegisterList Binary3RegisterOpAltA::defs(Instruction i) const { | 363 RegisterList Binary3RegisterOpAltA::defs(Instruction i) const { |
358 return RegisterList(d.reg(i)).Add(conditions.conds_if_updated(i)); | 364 return RegisterList(d.reg(i)).Add(conditions.conds_if_updated(i)); |
359 } | 365 } |
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2138 } | 2144 } |
2139 | 2145 |
2140 // InstructionBarrier | 2146 // InstructionBarrier |
2141 SafetyLevel InstructionBarrier::safety(Instruction i) const { | 2147 SafetyLevel InstructionBarrier::safety(Instruction i) const { |
2142 if (option.value(i) != 0xF) | 2148 if (option.value(i) != 0xF) |
2143 return FORBIDDEN_OPERANDS; | 2149 return FORBIDDEN_OPERANDS; |
2144 return UncondDecoder::safety(i); | 2150 return UncondDecoder::safety(i); |
2145 } | 2151 } |
2146 | 2152 |
2147 } // namespace nacl_arm_dec | 2153 } // namespace nacl_arm_dec |
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