ARM: Make use of d16-d31 when available.

src/arm/macro-assembler-arm.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 624 matching lines @@
 
 
 void MacroAssembler::PopSafepointRegisters() {
   const int num_unsaved = kNumSafepointRegisters - kNumSafepointSavedRegisters;
   ldm(ia_w, sp, kSafepointSavedRegisters);
   add(sp, sp, Operand(num_unsaved * kPointerSize));
 }
 
 
 void MacroAssembler::PushSafepointRegistersAndDoubles() {
+  ASSERT(!Serializer::enabled());  // Nbr of d-regs not known at snapshot time.
   PushSafepointRegisters();
-  sub(sp, sp, Operand(DwVfpRegister::kNumAllocatableRegisters *
+  sub(sp, sp, Operand(DwVfpRegister::NumAllocatableRegisters() *
                       kDoubleSize));
-  for (int i = 0; i < DwVfpRegister::kNumAllocatableRegisters; i++) {
+  for (int i = 0; i < DwVfpRegister::NumAllocatableRegisters(); i++) {
     vstr(DwVfpRegister::FromAllocationIndex(i), sp, i * kDoubleSize);
   }
 }
 
 
 void MacroAssembler::PopSafepointRegistersAndDoubles() {
-  for (int i = 0; i < DwVfpRegister::kNumAllocatableRegisters; i++) {
+  ASSERT(!Serializer::enabled());  // Nbr of d-regs not known at snapshot time.
+  for (int i = 0; i < DwVfpRegister::NumAllocatableRegisters(); i++) {
     vldr(DwVfpRegister::FromAllocationIndex(i), sp, i * kDoubleSize);
   }
-  add(sp, sp, Operand(DwVfpRegister::kNumAllocatableRegisters *
+  add(sp, sp, Operand(DwVfpRegister::NumAllocatableRegisters() *
                       kDoubleSize));
   PopSafepointRegisters();
 }
 
 void MacroAssembler::StoreToSafepointRegistersAndDoublesSlot(Register src,
                                                              Register dst) {
   str(src, SafepointRegistersAndDoublesSlot(dst));
 }
 
 
@@ skipping 14 matching lines @@
   return reg_code;
 }
 
 
 MemOperand MacroAssembler::SafepointRegisterSlot(Register reg) {
   return MemOperand(sp, SafepointRegisterStackIndex(reg.code()) * kPointerSize);
 }
 
 
 MemOperand MacroAssembler::SafepointRegistersAndDoublesSlot(Register reg) {
+  ASSERT(!Serializer::enabled());  // Nbr of d-regs not known at snapshot time.
   // General purpose registers are pushed last on the stack.
-  int doubles_size = DwVfpRegister::kNumAllocatableRegisters * kDoubleSize;
+  int doubles_size = DwVfpRegister::NumAllocatableRegisters() * kDoubleSize;
   int register_offset = SafepointRegisterStackIndex(reg.code()) * kPointerSize;
   return MemOperand(sp, doubles_size + register_offset);
 }
 
 
 void MacroAssembler::Ldrd(Register dst1, Register dst2,
                           const MemOperand& src, Condition cond) {
   ASSERT(src.rm().is(no_reg));
   ASSERT(!dst1.is(lr));  // r14.
   ASSERT_EQ(0, dst1.code() % 2);
@@ skipping 119 matching lines @@
   if (value.bits == zero.bits) {
     vmov(dst, kDoubleRegZero, cond);
   } else if (value.bits == minus_zero.bits) {
     vneg(dst, kDoubleRegZero, cond);
   } else {
     vmov(dst, imm, scratch, cond);
   }
 }
 
 
+void MacroAssembler::Vpop(Register base,
+                          const DwVfpRegister first,
+                          const DwVfpRegister last,
+                          Condition cond) {
+  ASSERT(CpuFeatures::IsEnabled(VFP2));
+  ASSERT_LE(first.code(), last.code());
+
+  const int first_code = first.code();
+  const int last_code = last.code();
+  const int count = last_code - first_code + 1;
+
+  if (count <= 16) {
+    vldm(ia_w, base, first, last, cond);
+  } else {
+    // Since we are increasing the address, load the first registers first.
+    ASSERT(first_code < 16 && last_code >= 16);
+    vldm(ia_w, base, first, d15, cond);
+    vldm(ia_w, base, d16, last, cond);
+  }
+}
+
+
+void MacroAssembler::Vpush(Register base,
+                           const DwVfpRegister first,
+                           const DwVfpRegister last,
+                           Condition cond) {
+  ASSERT(CpuFeatures::IsEnabled(VFP2));
+  ASSERT_LE(first.code(), last.code());
+
+  const int first_code = first.code();
+  const int last_code = last.code();
+  const int count = last_code - first_code + 1;
+
+  if (count <= 16) {
+    vstm(db_w, base, first, last, cond);
+  } else {
+    // Since we are decreasing the address, write the last registers first.
+    ASSERT(first_code < 16 && last_code >= 16);
+    vstm(db_w, base, d16, last, cond);
+    vstm(db_w, base, first, d15, cond);
+  }
+}
+
+
 void MacroAssembler::EnterFrame(StackFrame::Type type) {
   // r0-r3: preserved
   stm(db_w, sp, cp.bit() | fp.bit() | lr.bit());
   mov(ip, Operand(Smi::FromInt(type)));
   push(ip);
   mov(ip, Operand(CodeObject()));
   push(ip);
   add(fp, sp, Operand(3 * kPointerSize));  // Adjust FP to point to saved FP.
 }
 
@@ skipping 27 matching lines @@
   str(ip, MemOperand(fp, ExitFrameConstants::kCodeOffset));
 
   // Save the frame pointer and the context in top.
   mov(ip, Operand(ExternalReference(Isolate::kCEntryFPAddress, isolate())));
   str(fp, MemOperand(ip));
   mov(ip, Operand(ExternalReference(Isolate::kContextAddress, isolate())));
   str(cp, MemOperand(ip));
 
   // Optionally save all double registers.
   if (save_doubles) {
+    // Nbr of d-regs not known at snapshot time.
+    ASSERT(!Serializer::enabled());
     DwVfpRegister first = d0;
     DwVfpRegister last =
-        DwVfpRegister::from_code(DwVfpRegister::kNumRegisters - 1);
-    vstm(db_w, sp, first, last);
+        DwVfpRegister::from_code(DwVfpRegister::NumAvailableRegisters() - 1);
+    Vpush(sp, first, last);
     // Note that d0 will be accessible at
-    //   fp - 2 * kPointerSize - DwVfpRegister::kNumRegisters * kDoubleSize,
+    //   fp - 2 * kPointerSize -
+    //   DwVfpRegister::NumAvailableRegisters() * kDoubleSize,
     // since the sp slot and code slot were pushed after the fp.
   }
 
   // Reserve place for the return address and stack space and align the frame
   // preparing for calling the runtime function.
   const int frame_alignment = MacroAssembler::ActivationFrameAlignment();
   sub(sp, sp, Operand((stack_space + 1) * kPointerSize));
   if (frame_alignment > 0) {
     ASSERT(IsPowerOf2(frame_alignment));
     and_(sp, sp, Operand(-frame_alignment));
@@ skipping 34 matching lines @@
   // flag.
   return FLAG_sim_stack_alignment;
 #endif  // defined(V8_HOST_ARCH_ARM)
 }
 
 
 void MacroAssembler::LeaveExitFrame(bool save_doubles,
                                     Register argument_count) {
   // Optionally restore all double registers.
   if (save_doubles) {
+    // Nbr of d-regs not known at snapshot time.
+    ASSERT(!Serializer::enabled());
     // Calculate the stack location of the saved doubles and restore them.
     const int offset = 2 * kPointerSize;
-    sub(r3, fp, Operand(offset + DwVfpRegister::kNumRegisters * kDoubleSize));
+    sub(r3, fp, Operand(offset + DwVfpRegister::NumAvailableRegisters() *
+                        kDoubleSize));
     DwVfpRegister first = d0;
     DwVfpRegister last =
-        DwVfpRegister::from_code(DwVfpRegister::kNumRegisters - 1);
-    vldm(ia, r3, first, last);
+        DwVfpRegister::from_code(DwVfpRegister::NumAvailableRegisters() - 1);
+    Vpop(r3, first, last);
   }
 
   // Clear top frame.
   mov(r3, Operand(0, RelocInfo::NONE));
   mov(ip, Operand(ExternalReference(Isolate::kCEntryFPAddress, isolate())));
   str(r3, MemOperand(ip));
 
   // Restore current context from top and clear it in debug mode.
   mov(ip, Operand(ExternalReference(Isolate::kContextAddress, isolate())));
   ldr(cp, MemOperand(ip));
@@ skipping 2955 matching lines @@
 void CodePatcher::EmitCondition(Condition cond) {
   Instr instr = Assembler::instr_at(masm_.pc_);
   instr = (instr & ~kCondMask) | cond;
   masm_.emit(instr);
 }
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_ARM