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Side by Side Diff: src/arm/assembler-arm-inl.h

Issue 11428137: ARM: Make use of d16-d31 when available. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Rebase Created 7 years, 11 months ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions 5 // modification, are permitted provided that the following conditions
6 // are met: 6 // are met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
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51 if (CpuFeatures::IsSupported(VFP2)) { 51 if (CpuFeatures::IsSupported(VFP2)) {
52 return kMaxNumAllocatableRegisters; 52 return kMaxNumAllocatableRegisters;
53 } else { 53 } else {
54 return kMaxNumAllocatableRegisters - kGPRsPerNonVFP2Double; 54 return kMaxNumAllocatableRegisters - kGPRsPerNonVFP2Double;
55 } 55 }
56 } 56 }
57 57
58 58
59 int DwVfpRegister::NumRegisters() { 59 int DwVfpRegister::NumRegisters() {
60 if (CpuFeatures::IsSupported(VFP2)) { 60 if (CpuFeatures::IsSupported(VFP2)) {
61 return DwVfpRegister::kNumRegisters; 61 return CpuFeatures::IsSupported(VFP32DREGS) ? 32 : 16;
62 } else { 62 } else {
63 return 1; 63 return 1;
64 } 64 }
65 } 65 }
66 66
67 67
68 int DwVfpRegister::NumAllocatableRegisters() { 68 int DwVfpRegister::NumAllocatableRegisters() {
69 if (CpuFeatures::IsSupported(VFP2)) { 69 if (CpuFeatures::IsSupported(VFP2)) {
70 return DwVfpRegister::kMaxNumAllocatableRegisters; 70 return NumRegisters() - kNumReservedRegisters;
71 } else { 71 } else {
72 return 1; 72 return 1;
73 } 73 }
74 } 74 }
75 75
76 76
77 int DwVfpRegister::ToAllocationIndex(DwVfpRegister reg) { 77 int DwVfpRegister::ToAllocationIndex(DwVfpRegister reg) {
78 ASSERT(!reg.is(kDoubleRegZero)); 78 ASSERT(!reg.is(kDoubleRegZero));
79 ASSERT(!reg.is(kScratchDoubleReg)); 79 ASSERT(!reg.is(kScratchDoubleReg));
80 if (reg.code() > kDoubleRegZero.code()) {
81 return reg.code() - kNumReservedRegisters;
82 }
80 return reg.code(); 83 return reg.code();
81 } 84 }
82 85
83 86
87 DwVfpRegister DwVfpRegister::FromAllocationIndex(int index) {
88 ASSERT(index >= 0 && index < NumAllocatableRegisters());
89 ASSERT(kScratchDoubleReg.code() - kDoubleRegZero.code() ==
90 kNumReservedRegisters - 1);
91 if (index >= kDoubleRegZero.code()) {
92 return from_code(index + kNumReservedRegisters);
93 }
94 return from_code(index);
95 }
96
97
84 void RelocInfo::apply(intptr_t delta) { 98 void RelocInfo::apply(intptr_t delta) {
85 if (RelocInfo::IsInternalReference(rmode_)) { 99 if (RelocInfo::IsInternalReference(rmode_)) {
86 // absolute code pointer inside code object moves with the code object. 100 // absolute code pointer inside code object moves with the code object.
87 int32_t* p = reinterpret_cast<int32_t*>(pc_); 101 int32_t* p = reinterpret_cast<int32_t*>(pc_);
88 *p += delta; // relocate entry 102 *p += delta; // relocate entry
89 } 103 }
90 // We do not use pc relative addressing on ARM, so there is 104 // We do not use pc relative addressing on ARM, so there is
91 // nothing else to do. 105 // nothing else to do.
92 } 106 }
93 107
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526 540
527 541
528 void Assembler::set_target_address_at(Address pc, Address target) { 542 void Assembler::set_target_address_at(Address pc, Address target) {
529 set_target_pointer_at(pc, target); 543 set_target_pointer_at(pc, target);
530 } 544 }
531 545
532 546
533 } } // namespace v8::internal 547 } } // namespace v8::internal
534 548
535 #endif // V8_ARM_ASSEMBLER_ARM_INL_H_ 549 #endif // V8_ARM_ASSEMBLER_ARM_INL_H_
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