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Issue 11293061: Emit VMLA for multiply-add on ARM (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Address review comments Created 8 years, 1 month ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions 5 // modification, are permitted provided that the following conditions
6 // are met: 6 // are met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
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2383 // Dd = D:Vd; Dm=M:Vm; Dn=N:Vm. 2383 // Dd = D:Vd; Dm=M:Vm; Dn=N:Vm.
2384 // Instruction details available in ARM DDI 0406A, A8-784. 2384 // Instruction details available in ARM DDI 0406A, A8-784.
2385 // cond(31-28) | 11100(27-23)| D=?(22) | 10(21-20) | Vn(19-16) | 2385 // cond(31-28) | 11100(27-23)| D=?(22) | 10(21-20) | Vn(19-16) |
2386 // Vd(15-12) | 101(11-9) | sz(8)=1 | N(7)=0 | 0(6) | M=?(5) | 0(4) | Vm(3-0) 2386 // Vd(15-12) | 101(11-9) | sz(8)=1 | N(7)=0 | 0(6) | M=?(5) | 0(4) | Vm(3-0)
2387 ASSERT(CpuFeatures::IsEnabled(VFP2)); 2387 ASSERT(CpuFeatures::IsEnabled(VFP2));
2388 emit(cond | 0xE*B24 | 0x2*B20 | src1.code()*B16 | 2388 emit(cond | 0xE*B24 | 0x2*B20 | src1.code()*B16 |
2389 dst.code()*B12 | 0x5*B9 | B8 | src2.code()); 2389 dst.code()*B12 | 0x5*B9 | B8 | src2.code());
2390 } 2390 }
2391 2391
2392 2392
2393 void Assembler::vmla(const DwVfpRegister dst,
2394 const DwVfpRegister src1,
2395 const DwVfpRegister src2,
2396 const Condition cond) {
2397 // Instruction details available in ARM DDI 0406C.b, A8-892.
2398 // cond(31-28) | 11100(27-23) | D=?(22) | 00(21-20) | Vn(19-16) |
2399 // Vd(15-12) | 101(11-9) | sz(8)=1 | N=?(7) | op(6)=0 | M=?(5) | 0(4) |
2400 // Vm(3-0)
2401 unsigned x = (cond | 0x1C*B23 | src1.code()*B16 |
2402 dst.code()*B12 | 0x5*B9 | B8 | src2.code());
2403 emit(x);
2404 }
2405
2406
2393 void Assembler::vdiv(const DwVfpRegister dst, 2407 void Assembler::vdiv(const DwVfpRegister dst,
2394 const DwVfpRegister src1, 2408 const DwVfpRegister src1,
2395 const DwVfpRegister src2, 2409 const DwVfpRegister src2,
2396 const Condition cond) { 2410 const Condition cond) {
2397 // Dd = vdiv(Dn, Dm) double precision floating point division. 2411 // Dd = vdiv(Dn, Dm) double precision floating point division.
2398 // Dd = D:Vd; Dm=M:Vm; Dn=N:Vm. 2412 // Dd = D:Vd; Dm=M:Vm; Dn=N:Vm.
2399 // Instruction details available in ARM DDI 0406A, A8-584. 2413 // Instruction details available in ARM DDI 0406A, A8-584.
2400 // cond(31-28) | 11101(27-23)| D=?(22) | 00(21-20) | Vn(19-16) | 2414 // cond(31-28) | 11101(27-23)| D=?(22) | 00(21-20) | Vn(19-16) |
2401 // Vd(15-12) | 101(11-9) | sz(8)=1 | N(7)=? | 0(6) | M=?(5) | 0(4) | Vm(3-0) 2415 // Vd(15-12) | 101(11-9) | sz(8)=1 | N(7)=? | 0(6) | M=?(5) | 0(4) | Vm(3-0)
2402 ASSERT(CpuFeatures::IsEnabled(VFP2)); 2416 ASSERT(CpuFeatures::IsEnabled(VFP2));
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2770 2784
2771 // Since a constant pool was just emitted, move the check offset forward by 2785 // Since a constant pool was just emitted, move the check offset forward by
2772 // the standard interval. 2786 // the standard interval.
2773 next_buffer_check_ = pc_offset() + kCheckPoolInterval; 2787 next_buffer_check_ = pc_offset() + kCheckPoolInterval;
2774 } 2788 }
2775 2789
2776 2790
2777 } } // namespace v8::internal 2791 } } // namespace v8::internal
2778 2792
2779 #endif // V8_TARGET_ARCH_ARM 2793 #endif // V8_TARGET_ARCH_ARM
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