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1 /* | |
2 * Copyright (c) 2011 The Native Client Authors. All rights reserved. | |
3 * Use of this source code is governed by a BSD-style license that can be | |
4 * found in the LICENSE file. | |
5 */ | |
6 | |
7 #include <assert.h> | |
8 #include <stddef.h> | |
9 #include <stdio.h> | |
10 #include <stdlib.h> | |
11 #include <string.h> | |
12 | |
13 #include "native_client/src/include/elf32.h" | |
14 #include "native_client/src/shared/utils/types.h" | |
15 #include "native_client/src/trusted/validator_ragel/unreviewed/decoding.h" | |
16 | |
17 #include "native_client/src/trusted/validator_ragel/gen/decoder_x86_64_instructi
on_consts.h" | |
18 | |
19 %%{ | |
20 machine x86_64_decoder; | |
21 alphtype unsigned char; | |
22 variable p current_position; | |
23 variable pe end_of_data; | |
24 variable eof end_of_data; | |
25 variable cs current_state; | |
26 | |
27 include byte_machine "byte_machines.rl"; | |
28 | |
29 include prefix_actions | |
30 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl"; | |
31 include prefixes_parsing | |
32 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl"; | |
33 include rex_actions | |
34 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl"; | |
35 include rex_parsing | |
36 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl"; | |
37 include vex_actions_amd64 | |
38 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl"; | |
39 include vex_parsing_amd64 | |
40 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl"; | |
41 include att_suffix_actions | |
42 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl"; | |
43 include set_spurious_prefixes | |
44 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl"; | |
45 include displacement_fields_actions | |
46 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl"; | |
47 include displacement_fields_parsing | |
48 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl"; | |
49 include modrm_actions_amd64 | |
50 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl"; | |
51 include modrm_parsing_amd64 | |
52 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl"; | |
53 include operand_actions_amd64 | |
54 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl"; | |
55 include immediate_fields_actions | |
56 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl"; | |
57 include immediate_fields_parsing_amd64 | |
58 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl"; | |
59 include relative_fields_actions | |
60 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl"; | |
61 include relative_fields_parsing | |
62 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl"; | |
63 include cpuid_actions | |
64 "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl"; | |
65 | |
66 include decode_x86_64 "decoder_x86_64_instruction.rl"; | |
67 | |
68 main := (one_instruction | |
69 @{ | |
70 switch (instruction.rm.disp_type) { | |
71 case DISPNONE: instruction.rm.offset = 0; break; | |
72 case DISP8: instruction.rm.offset = (int8_t) *disp; break; | |
73 case DISP16: instruction.rm.offset = | |
74 (uint16_t) (disp[0] + 256U * disp[1]); | |
75 break; | |
76 case DISP32: instruction.rm.offset = (int32_t) | |
77 (disp[0] + 256U * (disp[1] + 256U * (disp[2] + 256U * (disp[3])))); | |
78 break; | |
79 case DISP64: instruction.rm.offset = (int64_t) | |
80 (*disp + 256ULL * (disp[1] + 256ULL * (disp[2] + 256ULL * (disp[3] + | |
81 256ULL * (disp[4] + 256ULL * (disp[5] + 256ULL * (disp[6] + 256ULL * | |
82 disp[7]))))))); | |
83 break; | |
84 } | |
85 switch (imm_operand) { | |
86 case IMMNONE: instruction.imm[0] = 0; break; | |
87 case IMM2: instruction.imm[0] = imm[0] & 0x03; break; | |
88 case IMM8: instruction.imm[0] = imm[0]; break; | |
89 case IMM16: instruction.imm[0] = (uint64_t) (*imm + 256U * (imm[1])); | |
90 break; | |
91 case IMM32: instruction.imm[0] = (uint64_t) | |
92 (imm[0] + 256U * (imm[1] + 256U * (imm[2] + 256U * (imm[3])))); | |
93 break; | |
94 case IMM64: instruction.imm[0] = (uint64_t) | |
95 (imm[0] + 256LL * (imm[1] + 256ULL * (imm[2] + 256ULL * (imm[3] + | |
96 256ULL * (imm[4] + 256ULL * (imm[5] + 256ULL * (imm[6] + 256ULL * | |
97 imm[7]))))))); | |
98 break; | |
99 } | |
100 switch (imm2_operand) { | |
101 case IMMNONE: instruction.imm[1] = 0; break; | |
102 case IMM2: instruction.imm[1] = imm2[0] & 0x03; break; | |
103 case IMM8: instruction.imm[1] = imm2[0]; break; | |
104 case IMM16: instruction.imm[1] = (uint64_t) | |
105 (imm2[0] + 256U * (imm2[1])); | |
106 break; | |
107 case IMM32: instruction.imm[1] = (uint64_t) | |
108 (imm2[0] + 256U * (imm2[1] + 256U * (imm2[2] + 256U * (imm2[3])))); | |
109 break; | |
110 case IMM64: instruction.imm[1] = (uint64_t) | |
111 (*imm2 + 256ULL * (imm2[1] + 256ULL * (imm2[2] + 256ULL * (imm2[3] + | |
112 256ULL * (imm2[4] + 256ULL * (imm2[5] + 256ULL * (imm2[6] + 256ULL * | |
113 imm2[7]))))))); | |
114 break; | |
115 } | |
116 process_instruction(instruction_start, current_position+1, &instruction, | |
117 userdata); | |
118 instruction_start = current_position + 1; | |
119 SET_DISP_TYPE(DISPNONE); | |
120 SET_IMM_TYPE(IMMNONE); | |
121 SET_IMM2_TYPE(IMMNONE); | |
122 SET_REX_PREFIX(FALSE); | |
123 SET_DATA16_PREFIX(FALSE); | |
124 SET_LOCK_PREFIX(FALSE); | |
125 SET_REPNZ_PREFIX(FALSE); | |
126 SET_REPZ_PREFIX(FALSE); | |
127 SET_BRANCH_NOT_TAKEN(FALSE); | |
128 SET_BRANCH_TAKEN(FALSE); | |
129 SET_VEX_PREFIX2(0xe0); | |
130 SET_VEX_PREFIX3(0x00); | |
131 SET_ATT_INSTRUCTION_SUFFIX(NULL); | |
132 instruction.prefix.data16_spurious = FALSE; | |
133 instruction.prefix.rex_b_spurious = FALSE; | |
134 instruction.prefix.rex_x_spurious = FALSE; | |
135 instruction.prefix.rex_r_spurious = FALSE; | |
136 instruction.prefix.rex_w_spurious = FALSE; | |
137 })* | |
138 $!{ process_error(current_position, userdata); | |
139 result = FALSE; | |
140 goto error_detected; | |
141 }; | |
142 | |
143 }%% | |
144 | |
145 %% write data; | |
146 | |
147 #define GET_REX_PREFIX() instruction.prefix.rex | |
148 #define SET_REX_PREFIX(P) instruction.prefix.rex = (P) | |
149 #define GET_VEX_PREFIX2() vex_prefix2 | |
150 #define SET_VEX_PREFIX2(P) vex_prefix2 = (P) | |
151 #define GET_VEX_PREFIX3() vex_prefix3 | |
152 #define SET_VEX_PREFIX3(P) vex_prefix3 = (P) | |
153 #define SET_DATA16_PREFIX(S) instruction.prefix.data16 = (S) | |
154 #define SET_LOCK_PREFIX(S) instruction.prefix.lock = (S) | |
155 #define SET_REPZ_PREFIX(S) instruction.prefix.repz = (S) | |
156 #define SET_REPNZ_PREFIX(S) instruction.prefix.repnz = (S) | |
157 #define SET_BRANCH_TAKEN(S) instruction.prefix.branch_taken = (S) | |
158 #define SET_BRANCH_NOT_TAKEN(S) instruction.prefix.branch_not_taken = (S) | |
159 #define SET_INSTRUCTION_NAME(N) instruction.name = (N) | |
160 #define GET_OPERAND_NAME(N) instruction.operands[(N)].name | |
161 #define SET_OPERAND_NAME(N, S) instruction.operands[(N)].name = (S) | |
162 #define SET_OPERAND_TYPE(N, S) instruction.operands[(N)].type = (S) | |
163 #define SET_OPERANDS_COUNT(N) instruction.operands_count = (N) | |
164 #define SET_MODRM_BASE(N) instruction.rm.base = (N) | |
165 #define SET_MODRM_INDEX(N) instruction.rm.index = (N) | |
166 #define SET_MODRM_SCALE(S) instruction.rm.scale = (S) | |
167 #define SET_DISP_TYPE(T) instruction.rm.disp_type = (T) | |
168 #define SET_DISP_PTR(P) disp = (P) | |
169 #define SET_IMM_TYPE(T) imm_operand = (T) | |
170 #define SET_IMM_PTR(P) imm = (P) | |
171 #define SET_IMM2_TYPE(T) imm2_operand = (T) | |
172 #define SET_IMM2_PTR(P) imm2 = (P) | |
173 #define SET_CPU_FEATURE(F) | |
174 #define SET_ATT_INSTRUCTION_SUFFIX(S) instruction.att_instruction_suffix = (S) | |
175 #define SET_SPURIOUS_DATA16() instruction.prefix.data16_spurious = TRUE; | |
176 #define SET_SPURIOUS_REX_B() \ | |
177 if (GET_REX_PREFIX() & REX_B) instruction.prefix.rex_b_spurious = TRUE; | |
178 #define SET_SPURIOUS_REX_X() \ | |
179 if (GET_REX_PREFIX() & REX_X) instruction.prefix.rex_x_spurious = TRUE; | |
180 #define SET_SPURIOUS_REX_R() \ | |
181 if (GET_REX_PREFIX() & REX_R) instruction.prefix.rex_r_spurious = TRUE; | |
182 #define SET_SPURIOUS_REX_W() \ | |
183 if (GET_REX_PREFIX() & REX_W) instruction.prefix.rex_w_spurious = TRUE; | |
184 | |
185 enum { | |
186 REX_B = 1, | |
187 REX_X = 2, | |
188 REX_R = 4, | |
189 REX_W = 8 | |
190 }; | |
191 | |
192 enum imm_mode { | |
193 IMMNONE, | |
194 IMM2, | |
195 IMM8, | |
196 IMM16, | |
197 IMM32, | |
198 IMM64 | |
199 }; | |
200 | |
201 int DecodeChunkAMD64(const uint8_t *data, size_t size, | |
202 ProcessInstructionFunc process_instruction, | |
203 ProcessDecodingErrorFunc process_error, | |
204 void *userdata) { | |
205 const uint8_t *current_position = data; | |
206 const uint8_t *end_of_data = data + size; | |
207 const uint8_t *disp = NULL; | |
208 const uint8_t *imm = NULL; | |
209 const uint8_t *imm2 = NULL; | |
210 const uint8_t *instruction_start = current_position; | |
211 uint8_t vex_prefix2 = 0xe0; | |
212 uint8_t vex_prefix3 = 0x00; | |
213 enum imm_mode imm_operand = IMMNONE; | |
214 enum imm_mode imm2_operand = IMMNONE; | |
215 struct Instruction instruction; | |
216 int result = TRUE; | |
217 | |
218 int current_state; | |
219 | |
220 SET_DISP_TYPE(DISPNONE); | |
221 SET_IMM_TYPE(IMMNONE); | |
222 SET_IMM2_TYPE(IMMNONE); | |
223 SET_REX_PREFIX(FALSE); | |
224 SET_DATA16_PREFIX(FALSE); | |
225 SET_LOCK_PREFIX(FALSE); | |
226 SET_REPNZ_PREFIX(FALSE); | |
227 SET_REPZ_PREFIX(FALSE); | |
228 SET_BRANCH_NOT_TAKEN(FALSE); | |
229 SET_BRANCH_TAKEN(FALSE); | |
230 SET_ATT_INSTRUCTION_SUFFIX(NULL); | |
231 instruction.prefix.data16_spurious = FALSE; | |
232 instruction.prefix.rex_b_spurious = FALSE; | |
233 instruction.prefix.rex_x_spurious = FALSE; | |
234 instruction.prefix.rex_r_spurious = FALSE; | |
235 instruction.prefix.rex_w_spurious = FALSE; | |
236 | |
237 %% write init; | |
238 %% write exec; | |
239 | |
240 error_detected: | |
241 return result; | |
242 } | |
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