[MIPS] Implementation of sel_ldr for MIPS architecture.

src/include/concurrency_ops.h

 /*
  * Copyright (c) 2012 The Native Client Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 
 #ifndef NATIVE_CLIENT_SRC_INCLUDE_CONCURRENCY_OPS_H_
 #define NATIVE_CLIENT_SRC_INCLUDE_CONCURRENCY_OPS_H_ 1
 
@@ skipping 18 matching lines @@
   /* Note that this depends on ARMv7. */
   __asm__ __volatile__("dsb");
 
   /*
    * We could support ARMv6 by instead using:
    * __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 5"
    *                      : : "r" (0) : "memory");
    */
 }
 
+#elif NACL_ARCH(NACL_BUILD_ARCH) == NACL_mips
+
+static INLINE void NaClWriteMemoryBarrier() {
+  __asm__ __volatile__("sync" : : : "memory");
+}
+
 #else
 
 #error "Define for other architectures"
 
 #endif
 
 
 static INLINE void NaClFlushCacheForDoublyMappedCode(uint8_t *writable_addr,
                                                      uint8_t *executable_addr,
                                                      size_t size) {
@@ skipping 28 matching lines @@
    * Give an error in case we ever target a non-gcc compiler for ARM
    * or for some other architecture that we might support in the
    * future.
    */
 # error "Don't know how to clear the icache on this architecture"
 #endif
 }
 
 
 #endif  /* NATIVE_CLIENT_SRC_INCLUDE_CONCURRENCY_OPS_H_ */