ARM validator: continue with extra_load_store_instructions.

src/trusted/validator_arm/baseline_classes.h

 /*
  * Copyright (c) 2012 The Native Client Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #ifndef NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_BASELINE_CLASSES_H_
 #define NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_BASELINE_CLASSES_H_
 
 #include "native_client/src/trusted/validator_arm/inst_classes.h"
 
+// TODO(jfb) Remove these forward declatations? They're only needed for
+//           friend classes which shouldn't be needed themselves.
+namespace nacl_arm_test {
+class LoadStore2RegisterImm8OpTester;
+class LoadStore2RegisterImm8DoubleOpTester;
+class LoadStore2RegisterImm12OpTester;
+class LoadStore3RegisterOpTester;
+class LoadStore3RegisterDoubleOpTester;
+class LoadStore3RegisterImm5OpTester;
+}  // namespace nacl_arm_test
+
 /*
  * Models the baseline "instruction classes" that capture what the
  * decoder produces.
  *
  * The baseline model is intentionally very close to the data formats
  * used in "ARM Architecture Reference Manual ARM*v7-A and ARM*v7-R
  * edition, Errata markup". For each data layout, there is a separate
  * class. In addition, the test infrastructure is based on testing if
  * the baseline class decoders do as expected (in terms of the
  * manual).
@@ skipping 126 matching lines @@
 // bits in the APSR.
 // MSR<c> <spec_reg>, #<const>
 // +--------+----------------+----+------------+------------------------+
 // |31302928|2726252423222120|1918|171615141312|1110 9 8 7 6 5 4 3 2 1 0|
 // +--------+----------------+----+------------+------------------------+
 // |  cond  |                |mask|            |         imm12          |
 // +--------+----------------+----+------------+------------------------+
 // Definitions:
 //    mask = Defines which parts of the APSR is set. When mask<1>=1,
 //           the N, Z, C, V, and Q bits (31:27) are updated. When
-//           mask<0>=1, the GE bits (3:0 and 19:16) are updated.
+//           mask<0>=1, the GE bits (19:16) are updated.
 // Note: If mask=3, then N, Z, C, V, Q, and GE bits are updated.
 // Note: mask=0 should not parse.
 class MoveImmediate12ToApsr : public ClassDecoder {
  public:
   // Interfaces for components in the instruction.
   static const Imm12Bits0To11Interface imm12;
   static const Imm2Bits18To19Interface mask;
   static const ConditionBits28To31Interface cond;
 
   // Methods for class.
@@ skipping 61 matching lines @@
 
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(BranchImmediate24);
 };
 
 // Defines a break point, which is also used to act as a constant pool header
 // if the constant is 0x7777.
 class BreakPointAndConstantPoolHead : public Immediate16Use {
  public:
   BreakPointAndConstantPoolHead() {}
+  virtual SafetyLevel safety(Instruction i) const;
   virtual bool is_literal_pool_head(Instruction i) const;
 
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(BreakPointAndConstantPoolHead);
 };
 
 // Models a branch to address in Rm.
 // Op<c> <Rm>
 // +--------+---------------------------------------------+--+--+--------+
 // |31302928|2726252423222212019181716151413121110 9 8 7 6| 5| 4| 3 2 1 0|
@@ skipping 362 matching lines @@
  public:
   static const Imm4Bits0To3Interface imm4L;
   static const Imm4Bits8To11Interface imm4H;
   static const RegBits12To15Interface t;
   static const RegBits16To19Interface n;
   static const WritesBit21Interface writes;
   static const AddOffsetBit23Interface direction;
   static const PrePostIndexingBit24Interface indexing;
   static const ConditionBits28To31Interface cond;
 
-  LoadStore2RegisterImm8Op() : ClassDecoder(), is_load_(false) {}
   virtual SafetyLevel safety(Instruction i) const;
   virtual RegisterList immediate_addressing_defs(Instruction i) const;
   virtual Register base_address_register(const Instruction i) const;
 
   bool HasWriteBack(const Instruction i) const {
     return indexing.IsPostIndexing(i) || writes.IsDefined(i);
   }
 
  protected:
+  // TODO(jfb) Remove friend? It looks like its usage of the protected
+  //           ctor shouldn't be.
+  friend class nacl_arm_test::LoadStore2RegisterImm8OpTester;
+  explicit LoadStore2RegisterImm8Op(bool is_load)
+      : ClassDecoder(), is_load_(is_load) {}
   bool is_load_;  // true if load (rather than store).
 
  private:
-  NACL_DISALLOW_COPY_AND_ASSIGN(LoadStore2RegisterImm8Op);
+  NACL_DISALLOW_DEFAULT_COPY_AND_ASSIGN(LoadStore2RegisterImm8Op);
 };
 
 // Defines the virtuals for a load immediate instruction.
 class Load2RegisterImm8Op : public LoadStore2RegisterImm8Op {
  public:
-  Load2RegisterImm8Op() : LoadStore2RegisterImm8Op() {
-    is_load_ = true;
+  Load2RegisterImm8Op() : LoadStore2RegisterImm8Op(true) {
   }
   virtual RegisterList defs(Instruction i) const;
   virtual bool offset_is_immediate(Instruction i) const;
 
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(Load2RegisterImm8Op);
 };
 
 // Defines the virtuals for a store immediate instruction.
 class Store2RegisterImm8Op : public LoadStore2RegisterImm8Op {
  public:
-  Store2RegisterImm8Op() : LoadStore2RegisterImm8Op() {
-    is_load_ = false;
+  Store2RegisterImm8Op() : LoadStore2RegisterImm8Op(false) {
   }
   virtual RegisterList defs(Instruction i) const;
 
  protected:
   NACL_DISALLOW_COPY_AND_ASSIGN(Store2RegisterImm8Op);
 };
 
 // Models a 2-register immediate load/store operation where the source/target
 // is double wide (i.e.  Rt and Rt2).
 class LoadStore2RegisterImm8DoubleOp
     : public LoadStore2RegisterImm8Op {
  public:
   // Interface for components in the instruction (and not inherited).
   static const RegBits12To15Plus1Interface t2;
 
-  LoadStore2RegisterImm8DoubleOp()
-      : LoadStore2RegisterImm8Op() {}
   virtual SafetyLevel safety(Instruction i) const;
 
+ protected:
+  // TODO(jfb) Remove friend? It looks like its usage of the protected
+  //           ctor shouldn't be.
+  friend class nacl_arm_test::LoadStore2RegisterImm8DoubleOpTester;
+  explicit LoadStore2RegisterImm8DoubleOp(bool is_load)
+      : LoadStore2RegisterImm8Op(is_load) {}
+
  private:
-  NACL_DISALLOW_COPY_AND_ASSIGN(LoadStore2RegisterImm8DoubleOp);
+  NACL_DISALLOW_DEFAULT_COPY_AND_ASSIGN(LoadStore2RegisterImm8DoubleOp);

[Karl, 2012/08/28 19:32:35]

Again, the Google C++ style guide suggests using DISALLOW_COPY_AND_ASSIGN, and
this implicitly also forces the omission of the default. Don't use the default
version.

[Please use jfb - chromium.org, 2012/08/28 22:19:21]

Should I leave it like that to be explicit?

 };
 
 // Defines the virtuals for a load immediate double instruction.
 class Load2RegisterImm8DoubleOp
     : public LoadStore2RegisterImm8DoubleOp {
  public:
-  Load2RegisterImm8DoubleOp() : LoadStore2RegisterImm8DoubleOp() {
-    is_load_ = true;
+  Load2RegisterImm8DoubleOp() : LoadStore2RegisterImm8DoubleOp(true) {
   }
   virtual RegisterList defs(Instruction i) const;
   virtual bool offset_is_immediate(Instruction i) const;
 
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(Load2RegisterImm8DoubleOp);
 };
 
 // Defines the virtuals for a store immediate double instruction.
 class Store2RegisterImm8DoubleOp
     : public LoadStore2RegisterImm8DoubleOp {
  public:
   Store2RegisterImm8DoubleOp()
-      : LoadStore2RegisterImm8DoubleOp() {
-    is_load_ = false;
+      : LoadStore2RegisterImm8DoubleOp(false) {
   }
   virtual RegisterList defs(Instruction i) const;
 
  protected:
   NACL_DISALLOW_COPY_AND_ASSIGN(Store2RegisterImm8DoubleOp);
 };
 
 // Models a 2-register load/store 12-bit immediate operation of the forms:
 // Op<c> <Rt>, [<Rn> {, #+/-<imm12>}]
 // Op<c> <Rt>, [<Rn>], #+/-<imm12>
@@ skipping 34 matching lines @@
 //    not model it as a special instruction.
 class LoadStore2RegisterImm12Op : public ClassDecoder {
  public:
   static const Imm12Bits0To11Interface imm12;
   static const RegBits12To15Interface t;
   static const RegBits16To19Interface n;
   static const WritesBit21Interface writes;
   static const AddOffsetBit23Interface direction;
   static const PrePostIndexingBit24Interface indexing;
   static const ConditionBits28To31Interface cond;
-  LoadStore2RegisterImm12Op() : ClassDecoder() , is_load_(false) {}
+
   virtual SafetyLevel safety(Instruction i) const;
   virtual RegisterList immediate_addressing_defs(Instruction i) const;
   virtual Register base_address_register(const Instruction i) const;
   bool HasWriteBack(const Instruction i) const {
     return indexing.IsPostIndexing(i) || writes.IsDefined(i);
   }
 
  protected:
+  // TODO(jfb) Remove friend? It looks like its usage of the protected
+  //           ctor shouldn't be.
+  friend class nacl_arm_test::LoadStore2RegisterImm12OpTester;
+  explicit LoadStore2RegisterImm12Op(bool is_load)
+      : ClassDecoder() , is_load_(is_load) {}
   bool is_load_;  // true if load (rather than store).
 
  private:
-  NACL_DISALLOW_COPY_AND_ASSIGN(LoadStore2RegisterImm12Op);
+  NACL_DISALLOW_DEFAULT_COPY_AND_ASSIGN(LoadStore2RegisterImm12Op);

[Karl, 2012/08/28 19:32:35]

Same here.

 };
 
 // Defines the virtuals for a load immediate instruction.
 class Load2RegisterImm12Op : public LoadStore2RegisterImm12Op {
  public:
-  Load2RegisterImm12Op() : LoadStore2RegisterImm12Op() {
-    is_load_ = true;
+  Load2RegisterImm12Op() : LoadStore2RegisterImm12Op(true) {
   }
   virtual RegisterList defs(Instruction i) const;
   virtual bool offset_is_immediate(Instruction i) const;
 
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(Load2RegisterImm12Op);
 };
 
 // Defines the virtuals for a store immediate instruction.
 // Note: See class LoadStore2RegisterImm12Op for more information
 // on how PUSH (i.e. when Rn=Sp && U=0 && W=1 && Imm12=4) is handled.
 class Store2RegisterImm12Op : public LoadStore2RegisterImm12Op {
  public:
-  Store2RegisterImm12Op() : LoadStore2RegisterImm12Op() {
-    is_load_ = false;
+  Store2RegisterImm12Op() : LoadStore2RegisterImm12Op(false) {
   }
   virtual RegisterList defs(Instruction i) const;
 
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(Store2RegisterImm12Op);
 };
 
 // Defines virtual for a store immediate instruction with the following
 // constraint:
 //     if wback && Rn=Rt then unpredictable.
@@ skipping 359 matching lines @@
  public:
   // Interfaces for components in the instruction.
   static const RegBits0To3Interface m;
   static const RegBits12To15Interface t;
   static const RegBits16To19Interface n;
   static const WritesBit21Interface writes;
   static const AddOffsetBit23Interface direction;
   static const PrePostIndexingBit24Interface indexing;
   static const ConditionBits28To31Interface cond;
 
-  LoadStore3RegisterOp() : ClassDecoder(), is_load_(false) {}
   virtual SafetyLevel safety(Instruction i) const;
   virtual Register base_address_register(const Instruction i) const;
   bool HasWriteBack(const Instruction i) const {
     return indexing.IsPostIndexing(i) || writes.IsDefined(i);
   }
 
  protected:
+  // TODO(jfb) Remove friend? It looks like its usage of the protected
+  //           ctor shouldn't be.
+  friend class nacl_arm_test::LoadStore3RegisterOpTester;
+  explicit LoadStore3RegisterOp(bool is_load)
+      : ClassDecoder(), is_load_(is_load) {}
   bool is_load_;  // true if load (rather than store).
 
  private:
-  NACL_DISALLOW_COPY_AND_ASSIGN(LoadStore3RegisterOp);
+  NACL_DISALLOW_DEFAULT_COPY_AND_ASSIGN(LoadStore3RegisterOp);

[Karl, 2012/08/28 19:32:35]

Same here.

 };
 
 // Defines the virtuals for a load register instruction.
 class Load3RegisterOp : public LoadStore3RegisterOp {
  public:
-  Load3RegisterOp() : LoadStore3RegisterOp() {
-    is_load_ = true;
+  Load3RegisterOp() : LoadStore3RegisterOp(true) {
   }
   virtual RegisterList defs(Instruction i) const;
 
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(Load3RegisterOp);
 };
 
 // Defines the virtuals for a store register instruction.
 class Store3RegisterOp : public LoadStore3RegisterOp {
  public:
-  Store3RegisterOp() : LoadStore3RegisterOp() {
-    is_load_ = false;
+  Store3RegisterOp() : LoadStore3RegisterOp(false) {
   }
   virtual RegisterList defs(Instruction i) const;
 
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(Store3RegisterOp);
 };
 
 // Models a 3-register load/store operation where the source/target is double
 //  wide (i.e. Rt and Rt2).
 class LoadStore3RegisterDoubleOp : public LoadStore3RegisterOp {
  public:
   // Interface for components in the instruction (and not inherited).
   static const RegBits12To15Plus1Interface t2;
 
-  LoadStore3RegisterDoubleOp() : LoadStore3RegisterOp() {}
   virtual SafetyLevel safety(Instruction i) const;
 
+ protected:
+  // TODO(jfb) Remove friend? It looks like its usage of the protected
+  //           ctor shouldn't be.
+  friend class nacl_arm_test::LoadStore3RegisterDoubleOpTester;
+  explicit LoadStore3RegisterDoubleOp(bool is_load)
+      : LoadStore3RegisterOp(is_load) {}
+
  private:
-  NACL_DISALLOW_COPY_AND_ASSIGN(LoadStore3RegisterDoubleOp);
+  NACL_DISALLOW_DEFAULT_COPY_AND_ASSIGN(LoadStore3RegisterDoubleOp);

[Karl, 2012/08/28 19:32:35]

Same here.

 };
 
 // Defines the virtuals for a load double register instruction
 class Load3RegisterDoubleOp : public LoadStore3RegisterDoubleOp {
  public:
-  Load3RegisterDoubleOp() : LoadStore3RegisterDoubleOp() {
-    is_load_ = true;
+  Load3RegisterDoubleOp() : LoadStore3RegisterDoubleOp(true) {
   }
   virtual RegisterList defs(Instruction i) const;
 
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(Load3RegisterDoubleOp);
 };
 
 // Defines the virtuals for s store double register instruction.
 class Store3RegisterDoubleOp : public LoadStore3RegisterDoubleOp {
  public:
-  Store3RegisterDoubleOp() : LoadStore3RegisterDoubleOp() {
-    is_load_ = false;
+  Store3RegisterDoubleOp() : LoadStore3RegisterDoubleOp(false) {
   }
   virtual RegisterList defs(Instruction i) const;
 
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(Store3RegisterDoubleOp);
 };
 
 // Models a 2-register store (exclusive) operation with a register to hold the
 // status of the update.
 // Op<c><q> <Rd>, <Rt>, [<Rn>]
@@ skipping 73 matching lines @@
   static const RegBits0To3Interface m;
   static const RegBits12To15Interface t;
   static const RegBits16To19Interface n;
   static const WritesBit21Interface writes;
   static const AddOffsetBit23Interface direction;
   static const PrePostIndexingBit24Interface indexing;
   static const ConditionBits28To31Interface cond;
   static const ShiftTypeBits5To6Interface shift_type;
   static const Imm5Bits7To11Interface imm;
 
-  LoadStore3RegisterImm5Op() : ClassDecoder(), is_load_(false) {}
   virtual SafetyLevel safety(Instruction i) const;
   virtual Register base_address_register(const Instruction i) const;
 
   bool HasWriteBack(const Instruction i) const {
     return indexing.IsPostIndexing(i) || writes.IsDefined(i);
   }
 
   // The immediate value stored in the instruction.
   uint32_t ImmediateValue(const Instruction& i) const {
     return shift_type.DecodeImmShift(i, imm.value(i));
   }
 
  protected:
+  // TODO(jfb) Remove friend? It looks like its usage of the protected
+  //           ctor shouldn't be.
+  friend class nacl_arm_test::LoadStore3RegisterImm5OpTester;
+  explicit LoadStore3RegisterImm5Op(bool is_load)
+      : ClassDecoder(), is_load_(is_load) {}
   bool is_load_;  // true if load (rather than store).
 
  private:
-  NACL_DISALLOW_COPY_AND_ASSIGN(LoadStore3RegisterImm5Op);
+  NACL_DISALLOW_DEFAULT_COPY_AND_ASSIGN(LoadStore3RegisterImm5Op);

[Karl, 2012/08/28 19:32:35]

Same here.

 };
 
 // Defines the virtuals for a load register instruction.
 class Load3RegisterImm5Op : public LoadStore3RegisterImm5Op {
  public:
-  Load3RegisterImm5Op() : LoadStore3RegisterImm5Op() {
-    is_load_ = true;
+  Load3RegisterImm5Op() : LoadStore3RegisterImm5Op(true) {
   }
   virtual RegisterList defs(Instruction i) const;
 
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(Load3RegisterImm5Op);
 };
 
 // Defines the virtuals for a store register instruction.
 class Store3RegisterImm5Op : public LoadStore3RegisterImm5Op {
  public:
-  Store3RegisterImm5Op() : LoadStore3RegisterImm5Op() {
-    is_load_ = false;
+  Store3RegisterImm5Op() : LoadStore3RegisterImm5Op(false) {
   }
   virtual RegisterList defs(Instruction i) const;
 
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(Store3RegisterImm5Op);
 };
 
 // Models a 2-register immediate-shifted unary operation of the form:
 // Op(S)<c> <Rd>, <Rm> {,<shift>}
 // +--------+--------------+--+--------+--------+----------+----+--+--------+
@@ skipping 608 matching lines @@
   virtual SafetyLevel safety(Instruction i) const;
 
   uint32_t be_value(const Instruction& i) const {
     return (b.value(i) << 1) | e.value(i);
   }
 };
 
 }  // namespace nacl_arm_dec
 
 #endif  // NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_BASELINE_CLASSES_H_