ARM validator: continue with extra_load_store_instructions.

src/trusted/validator_arm/actual_classes.h

 /*
  * Copyright (c) 2012 The Native Client Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #ifndef NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_ACTUAL_CLASSES_H_
 #define NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_ACTUAL_CLASSES_H_
 
 #include "native_client/src/trusted/validator_arm/inst_classes.h"
@@ skipping 434 matching lines @@
 // Defines a based memory load with writeback.
 class LoadBasedMemoryWithWriteBack : public LoadBasedMemory {
  public:
   // Interfaces for components defining writeback.
   static const WritesBit21Interface writes;
   static const PrePostIndexingBit24Interface indexing;
   bool HasWriteBack(const Instruction i) const {
     return indexing.IsPostIndexing(i) || writes.IsDefined(i);
   }
 
-  LoadBasedMemoryWithWriteBack() {}
   virtual SafetyLevel safety(Instruction i) const;
   virtual RegisterList defs(Instruction i) const;
 
+ protected:
+  LoadBasedMemoryWithWriteBack() {}
+
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(LoadBasedMemoryWithWriteBack);
 };
 
 // Defines a based memory load on register Rn, assuming it can
 // be modified by a small literal offset, and optionally, the
 // value defined in register Rm.
 class LoadBasedOffsetMemory : public LoadBasedMemoryWithWriteBack {
  public:
   // The offset register.
@@ skipping 74 matching lines @@
 // Defines a based memory store from register Rt(15, 12), with writeback.
 class StoreBasedMemoryWithWriteBack : public BasedAddressUsingRn {
  public:
   static const RegBits12To15Interface t;
   static const WritesBit21Interface writes;
   static const PrePostIndexingBit24Interface indexing;
   bool HasWriteBack(const Instruction i) const {
     return indexing.IsPostIndexing(i) || writes.IsDefined(i);
   }
 
-  StoreBasedMemoryWithWriteBack() {}
   virtual SafetyLevel safety(Instruction i) const;
   virtual RegisterList defs(Instruction i) const;
 
+ protected:
+  StoreBasedMemoryWithWriteBack() {}
+
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(StoreBasedMemoryWithWriteBack);
 };
 
 // Defines a based memory store using register Rn, assuming it can
 // be modified by a small literal offset, and optionally, the value
 // defined in register Rm.
 class StoreBasedOffsetMemory : public StoreBasedMemoryWithWriteBack {
  public:
   static const RegBits0To3Interface m;
@@ skipping 129 matching lines @@
   NACL_DISALLOW_COPY_AND_ASSIGN(Roadblock);
 };
 
 // BKPT
 // We model this mostly so we can use it to recognize literal pools -- untrusted
 // code isn't expected to use it, but it's not unsafe, and there are cases where
 // we may generate it.
 class Breakpoint : public Roadblock {
  public:
   Breakpoint() {}
+  virtual SafetyLevel safety(Instruction i) const;
   virtual bool is_literal_pool_head(Instruction i) const;
 
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(Breakpoint);
 };
 
 // Models the Pack/Saturate/Reverse instructions, which
 //  - Write a register identified by 15:12,
 //  - Are not permitted to affect r15,
 //  - Always set flags.
@@ skipping 413 matching lines @@
   virtual RegisterList defs(Instruction i) const;
   virtual bool clears_bits(Instruction i, uint32_t mask) const;
 
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(Unary1RegisterBitRange);
 };
 
 }  // namespace nacl_arm_dec
 
 #endif  // NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_ACTUAL_CLASSES_H_