ARM validator: continue with extra_load_store_instructions.

src/trusted/validator_arm/inst_classes_testers.cc

 /*
  * Copyright (c) 2012 The Native Client Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 #ifndef NACL_TRUSTED_BUT_NOT_TCB
 #error This file is not meant for use in the TCB
 #endif
 
 #include "native_client/src/trusted/validator_arm/inst_classes_testers.h"
@@ skipping 1033 matching lines @@
   // Other ARM constraints about this instruction.
   EXPECT_TRUE(expected_decoder_.t.IsEven(inst));
   EXPECT_FALSE(expected_decoder_.t2.reg(inst).Equals(kRegisterPc))
       << "Expected UNPREDICTABLE for " << InstContents();
 
   return true;
 }
 
 // LoadStore2RegisterImm8OpTester
 LoadStore2RegisterImm8OpTester::LoadStore2RegisterImm8OpTester(
-    const NamedClassDecoder& decoder) : CondDecoderTester(decoder) {}
+    const NamedClassDecoder& decoder)
+    : CondDecoderTester(decoder),
+      // TODO(jfb) Assuming this is a load seems wrong.
+      expected_decoder_(true) {}
 
 bool LoadStore2RegisterImm8OpTester::
 PassesParsePreconditions(Instruction inst,
                          const NamedClassDecoder& decoder) {
   // Should not parse if P=0 && W=1.
   NC_PRECOND(!(expected_decoder_.indexing.IsPostIndexing(inst) &&
                expected_decoder_.writes.IsDefined(inst)));
   return CondDecoderTester::PassesParsePreconditions(inst, decoder);
 }
 
@@ skipping 59 matching lines @@
   // Check that we don't parse when Rn=15.
   if (expected_decoder_.n.reg(inst).Equals(kRegisterPc)) {
     NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
   }
   return LoadStore2RegisterImm8OpTester::ApplySanityChecks(inst, decoder);
 }
 
 // LoadStore2RegisterImm8DoubleOpTester
 LoadStore2RegisterImm8DoubleOpTester::
 LoadStore2RegisterImm8DoubleOpTester(const NamedClassDecoder& decoder)
-    : LoadStore2RegisterImm8OpTester(decoder) {}
+    : LoadStore2RegisterImm8OpTester(decoder),
+      // TODO(jfb) Assuming this is a load seems wrong.
+      expected_decoder_(true) {}
 
 bool LoadStore2RegisterImm8DoubleOpTester::
 ApplySanityChecks(Instruction inst,
                   const NamedClassDecoder& decoder) {
   NC_PRECOND(LoadStore2RegisterImm8OpTester::
              ApplySanityChecks(inst, decoder));
 
   // Check Registers and flags used.
   EXPECT_EQ(expected_decoder_.t.number(inst) + 1,
             expected_decoder_.t2.number(inst));
@@ skipping 38 matching lines @@
   if (expected_decoder_.n.reg(inst).Equals(kRegisterPc)) {
     NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
   }
 
   return LoadStore2RegisterImm8DoubleOpTester::
       ApplySanityChecks(inst, decoder);
 }
 
 // LoadStore2RegisterImm12OpTester
 LoadStore2RegisterImm12OpTester::LoadStore2RegisterImm12OpTester(
-    const NamedClassDecoder& decoder) : CondDecoderTester(decoder) {}
+    const NamedClassDecoder& decoder)
+  : CondDecoderTester(decoder),
+    // TODO(jfb) Assuming this is a load seems wrong.
+    expected_decoder_(true) {}
 
 bool LoadStore2RegisterImm12OpTester::
 PassesParsePreconditions(Instruction inst,
                          const NamedClassDecoder& decoder) {
   // Should not parse if P=0 && W=1.
   NC_PRECOND(!(expected_decoder_.indexing.IsPostIndexing(inst) &&
                expected_decoder_.writes.IsDefined(inst)));
   return CondDecoderTester::PassesParsePreconditions(inst, decoder);
 }
 
@@ skipping 202 matching lines @@
       LoadStoreVectorOpTester::ApplySanityChecks(inst, decoder));
 
   // Other constraints about this instruction.
   EXPECT_FALSE(expected_decoder_.n.reg(inst).Equals(kRegisterPc));
 
   return true;
 }
 
 // LoadStore3RegisterOpTester
 LoadStore3RegisterOpTester::LoadStore3RegisterOpTester(
-    const NamedClassDecoder& decoder) : CondDecoderTester(decoder) {}
+    const NamedClassDecoder& decoder)
+    : CondDecoderTester(decoder),
+      // TODO(jfb) Assuming this is a load seems wrong.
+      expected_decoder_(true) {}
 
 bool LoadStore3RegisterOpTester::
 PassesParsePreconditions(Instruction inst,
                          const NamedClassDecoder& decoder) {
   // Should not parse if P=0 && W=1.
   NC_PRECOND(!(expected_decoder_.indexing.IsPostIndexing(inst) &&
                expected_decoder_.writes.IsDefined(inst)));
   return CondDecoderTester::PassesParsePreconditions(inst, decoder);
 }
 
@@ skipping 40 matching lines @@
 
   EXPECT_FALSE(ExpectedDecoder().defs(inst).Contains(kRegisterPc))
       << "Expected FORBIDDEN_OPERANDS for " << InstContents();
 
   return true;
 }
 
 // LoadStore3RegisterDoubleOpTester
 LoadStore3RegisterDoubleOpTester::
 LoadStore3RegisterDoubleOpTester(const NamedClassDecoder& decoder)
-    : LoadStore3RegisterOpTester(decoder) {
-}
+    : LoadStore3RegisterOpTester(decoder),
+      // TODO(jfb) Assuming this is a load seems wrong.
+      expected_decoder_(true) {}
 
 bool LoadStore3RegisterDoubleOpTester::
 ApplySanityChecks(Instruction inst,
                   const NamedClassDecoder& decoder) {
   NC_PRECOND(LoadStore3RegisterOpTester::ApplySanityChecks(inst, decoder));
 
   // Check Registers and flags used.
   EXPECT_EQ(expected_decoder_.t.number(inst) + 1,
             expected_decoder_.t2.number(inst));
 
@@ skipping 68 matching lines @@
       << "Expected UNPREDICTABLE for " << InstContents();
   EXPECT_FALSE(expected_decoder_.d.reg(inst).
                Equals(expected_decoder_.t2.reg(inst)))
       << "Expected UNPREDICTABLE for " << InstContents();
 
   return true;
 }
 
 // LoadStore3RegisterImm5OpTester
 LoadStore3RegisterImm5OpTester::LoadStore3RegisterImm5OpTester(
-    const NamedClassDecoder& decoder) : CondDecoderTester(decoder) {}
+    const NamedClassDecoder& decoder)
+    : CondDecoderTester(decoder),
+      // TODO(jfb) Assuming this is a load seems wrong.
+      expected_decoder_(true) {}
 
 bool LoadStore3RegisterImm5OpTester::
 ApplySanityChecks(Instruction inst,
                   const NamedClassDecoder& decoder) {
   // Should not parse if P=0 && W=1.
   if (expected_decoder_.indexing.IsPostIndexing(inst) &&
       expected_decoder_.writes.IsDefined(inst)) {
     NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
   }
 
@@ skipping 631 matching lines @@
       << "Expected Unpredictable for " << InstContents();
   EXPECT_FALSE(expected_decoder_.is_two_regs.IsDefined(inst)
                && !expected_decoder_.vd.IsEven(inst));
   EXPECT_NE(expected_decoder_.be_value(inst),
             static_cast<uint32_t>(0x3));
 
   return true;
 }
 
 }  // namespace nacl_arm_test