ARM validator: continue with extra_load_store_instructions.

src/trusted/validator_arm/gen/arm32_decode_tests.cc

 /*
  * Copyright 2012 The Native Client Authors.  All rights reserved.
  * Use of this source code is governed by a BSD-style license that can
  * be found in the LICENSE file.
  */
 
 // DO NOT EDIT: GENERATED CODE
 
 #ifndef NACL_TRUSTED_BUT_NOT_TCB
 #error This file is not meant for use in the TCB
@@ skipping 321 matching lines @@
      const NamedClassDecoder& decoder) {
 
   // Check that row patterns apply to pattern being checked.'
   if ((inst.Bits() & 0x03000000) != 0x03000000 /* op(25:20) == ~11xxxx */) return false;
 
   // Check other preconditions defined for the base decoder.
   return BranchImmediate24Tester::
       PassesParsePreconditions(inst, decoder);
 }
 
+class UnsafeCondNopTesterop_25Is0_op1_24To20Is0xx1x_op2_7To4Is1011
+    : public UnsafeCondNopTester {
+ public:
+  UnsafeCondNopTesterop_25Is0_op1_24To20Is0xx1x_op2_7To4Is1011(const NamedClassDecoder& decoder)
+    : UnsafeCondNopTester(decoder) {}
+  virtual bool PassesParsePreconditions(
+      nacl_arm_dec::Instruction inst,
+      const NamedClassDecoder& decoder);
+
+};
+
+bool UnsafeCondNopTesterop_25Is0_op1_24To20Is0xx1x_op2_7To4Is1011
+::PassesParsePreconditions(
+     nacl_arm_dec::Instruction inst,
+     const NamedClassDecoder& decoder) {
+
+  // Check that row patterns apply to pattern being checked.'
+  if ((inst.Bits() & 0x02000000) != 0x00000000 /* op(25:25) == ~0 */) return false;
+  if ((inst.Bits() & 0x01200000) != 0x00200000 /* op1(24:20) == ~0xx1x */) return false;
+  if ((inst.Bits() & 0x000000F0) != 0x000000B0 /* op2(7:4) == ~1011 */) return false;
+
+  // Check other preconditions defined for the base decoder.
+  return UnsafeCondNopTester::
+      PassesParsePreconditions(inst, decoder);
+}
+
+class UnsafeCondNopTesterop_25Is0_op1_24To20Is0xx1x_op2_7To4Is11x1
+    : public UnsafeCondNopTester {
+ public:
+  UnsafeCondNopTesterop_25Is0_op1_24To20Is0xx1x_op2_7To4Is11x1(const NamedClassDecoder& decoder)
+    : UnsafeCondNopTester(decoder) {}
+  virtual bool PassesParsePreconditions(
+      nacl_arm_dec::Instruction inst,
+      const NamedClassDecoder& decoder);
+
+};
+
+bool UnsafeCondNopTesterop_25Is0_op1_24To20Is0xx1x_op2_7To4Is11x1
+::PassesParsePreconditions(
+     nacl_arm_dec::Instruction inst,
+     const NamedClassDecoder& decoder) {
+
+  // Check that row patterns apply to pattern being checked.'
+  if ((inst.Bits() & 0x02000000) != 0x00000000 /* op(25:25) == ~0 */) return false;
+  if ((inst.Bits() & 0x01200000) != 0x00200000 /* op1(24:20) == ~0xx1x */) return false;
+  if ((inst.Bits() & 0x000000D0) != 0x000000D0 /* op2(7:4) == ~11x1 */) return false;
+
+  // Check other preconditions defined for the base decoder.
+  return UnsafeCondNopTester::
+      PassesParsePreconditions(inst, decoder);
+}
+
 class Unary1RegisterImmediateOpTesterop_25Is1_op1_24To20Is10000RegsNotPc
     : public Unary1RegisterImmediateOpTesterRegsNotPc {
  public:
   Unary1RegisterImmediateOpTesterop_25Is1_op1_24To20Is10000RegsNotPc(const NamedClassDecoder& decoder)
     : Unary1RegisterImmediateOpTesterRegsNotPc(decoder) {}
   virtual bool PassesParsePreconditions(
       nacl_arm_dec::Instruction inst,
       const NamedClassDecoder& decoder);
 
 };
@@ skipping 128 matching lines @@
 
   // Check that row patterns apply to pattern being checked.'
   if ((inst.Bits() & 0x01F00000) != 0x00400000 /* op(24:20) == ~00100 */) return false;
   if ((inst.Bits() & 0x000F0000) != 0x000F0000 /* Rn(19:16) == ~1111 */) return false;
 
   // Check other preconditions defined for the base decoder.
   return Unary1RegisterImmediateOpTester::
       PassesParsePreconditions(inst, decoder);
 }
 
+class UnsafeCondNopTesterop_24To20Is00101_Rn_19To16Is1111
+    : public UnsafeCondNopTester {
+ public:
+  UnsafeCondNopTesterop_24To20Is00101_Rn_19To16Is1111(const NamedClassDecoder& decoder)
+    : UnsafeCondNopTester(decoder) {}
+  virtual bool PassesParsePreconditions(
+      nacl_arm_dec::Instruction inst,
+      const NamedClassDecoder& decoder);
+
+};
+
+bool UnsafeCondNopTesterop_24To20Is00101_Rn_19To16Is1111
+::PassesParsePreconditions(
+     nacl_arm_dec::Instruction inst,
+     const NamedClassDecoder& decoder) {
+
+  // Check that row patterns apply to pattern being checked.'
+  if ((inst.Bits() & 0x01F00000) != 0x00500000 /* op(24:20) == ~00101 */) return false;
+  if ((inst.Bits() & 0x000F0000) != 0x000F0000 /* Rn(19:16) == ~1111 */) return false;
+
+  // Check other preconditions defined for the base decoder.
+  return UnsafeCondNopTester::
+      PassesParsePreconditions(inst, decoder);
+}
+
 class Binary2RegisterImmediateOpTesterop_24To20Is0011xNotRdIsPcAndS
     : public Binary2RegisterImmediateOpTesterNotRdIsPcAndS {
  public:
   Binary2RegisterImmediateOpTesterop_24To20Is0011xNotRdIsPcAndS(const NamedClassDecoder& decoder)
     : Binary2RegisterImmediateOpTesterNotRdIsPcAndS(decoder) {}
   virtual bool PassesParsePreconditions(
       nacl_arm_dec::Instruction inst,
       const NamedClassDecoder& decoder);
 
 };
@@ skipping 54 matching lines @@
 
   // Check that row patterns apply to pattern being checked.'
   if ((inst.Bits() & 0x01F00000) != 0x00800000 /* op(24:20) == ~01000 */) return false;
   if ((inst.Bits() & 0x000F0000) != 0x000F0000 /* Rn(19:16) == ~1111 */) return false;
 
   // Check other preconditions defined for the base decoder.
   return Unary1RegisterImmediateOpTester::
       PassesParsePreconditions(inst, decoder);
 }
 
+class UnsafeCondNopTesterop_24To20Is01001_Rn_19To16Is1111
+    : public UnsafeCondNopTester {
+ public:
+  UnsafeCondNopTesterop_24To20Is01001_Rn_19To16Is1111(const NamedClassDecoder& decoder)
+    : UnsafeCondNopTester(decoder) {}
+  virtual bool PassesParsePreconditions(
+      nacl_arm_dec::Instruction inst,
+      const NamedClassDecoder& decoder);
+
+};
+
+bool UnsafeCondNopTesterop_24To20Is01001_Rn_19To16Is1111
+::PassesParsePreconditions(
+     nacl_arm_dec::Instruction inst,
+     const NamedClassDecoder& decoder) {
+
+  // Check that row patterns apply to pattern being checked.'
+  if ((inst.Bits() & 0x01F00000) != 0x00900000 /* op(24:20) == ~01001 */) return false;
+  if ((inst.Bits() & 0x000F0000) != 0x000F0000 /* Rn(19:16) == ~1111 */) return false;
+
+  // Check other preconditions defined for the base decoder.
+  return UnsafeCondNopTester::
+      PassesParsePreconditions(inst, decoder);
+}
+
 class Binary2RegisterImmediateOpTesterop_24To20Is0101xNotRdIsPcAndS
     : public Binary2RegisterImmediateOpTesterNotRdIsPcAndS {
  public:
   Binary2RegisterImmediateOpTesterop_24To20Is0101xNotRdIsPcAndS(const NamedClassDecoder& decoder)
     : Binary2RegisterImmediateOpTesterNotRdIsPcAndS(decoder) {}
   virtual bool PassesParsePreconditions(
       nacl_arm_dec::Instruction inst,
       const NamedClassDecoder& decoder);
 
 };
@@ skipping 2192 matching lines @@
   if ((inst.Bits() & 0x02000000) != 0x02000000 /* A(25:25) == ~1 */) return false;
   if ((inst.Bits() & 0x00500000) != 0x00000000 /* op1(24:20) == ~xx0x0 */) return false;
   if ((inst.Bits() & 0x00000010) != 0x00000000 /* B(4:4) == ~0 */) return false;
   if ((inst.Bits() & 0x01700000) == 0x00200000 /* op1_repeated(24:20) == 0x010 */) return false;
 
   // Check other preconditions defined for the base decoder.
   return LoadStore3RegisterImm5OpTester::
       PassesParsePreconditions(inst, decoder);
 }
 
+class UnsafeCondNopTesterA_25Is0_op1_24To20Is0x010
+    : public UnsafeCondNopTester {
+ public:
+  UnsafeCondNopTesterA_25Is0_op1_24To20Is0x010(const NamedClassDecoder& decoder)
+    : UnsafeCondNopTester(decoder) {}
+  virtual bool PassesParsePreconditions(
+      nacl_arm_dec::Instruction inst,
+      const NamedClassDecoder& decoder);
+
+};
+
+bool UnsafeCondNopTesterA_25Is0_op1_24To20Is0x010
+::PassesParsePreconditions(
+     nacl_arm_dec::Instruction inst,
+     const NamedClassDecoder& decoder) {
+
+  // Check that row patterns apply to pattern being checked.'
+  if ((inst.Bits() & 0x02000000) != 0x00000000 /* A(25:25) == ~0 */) return false;
+  if ((inst.Bits() & 0x01700000) != 0x00200000 /* op1(24:20) == ~0x010 */) return false;
+
+  // Check other preconditions defined for the base decoder.
+  return UnsafeCondNopTester::
+      PassesParsePreconditions(inst, decoder);
+}
+
+class UnsafeCondNopTesterA_25Is1_op1_24To20Is0x010_B_4Is0
+    : public UnsafeCondNopTester {
+ public:
+  UnsafeCondNopTesterA_25Is1_op1_24To20Is0x010_B_4Is0(const NamedClassDecoder& decoder)
+    : UnsafeCondNopTester(decoder) {}
+  virtual bool PassesParsePreconditions(
+      nacl_arm_dec::Instruction inst,
+      const NamedClassDecoder& decoder);
+
+};
+
+bool UnsafeCondNopTesterA_25Is1_op1_24To20Is0x010_B_4Is0
+::PassesParsePreconditions(
+     nacl_arm_dec::Instruction inst,
+     const NamedClassDecoder& decoder) {
+
+  // Check that row patterns apply to pattern being checked.'
+  if ((inst.Bits() & 0x02000000) != 0x02000000 /* A(25:25) == ~1 */) return false;
+  if ((inst.Bits() & 0x01700000) != 0x00200000 /* op1(24:20) == ~0x010 */) return false;
+  if ((inst.Bits() & 0x00000010) != 0x00000000 /* B(4:4) == ~0 */) return false;
+
+  // Check other preconditions defined for the base decoder.
+  return UnsafeCondNopTester::
+      PassesParsePreconditions(inst, decoder);
+}
+
 class LoadStore2RegisterImm12OpTesterA_25Is0_op1_24To20Isxx0x1_NotRn_19To16Is1111_Notop1_repeated_24To20Is0x011NotRnIsPc
     : public LoadStore2RegisterImm12OpTesterNotRnIsPc {
  public:
   LoadStore2RegisterImm12OpTesterA_25Is0_op1_24To20Isxx0x1_NotRn_19To16Is1111_Notop1_repeated_24To20Is0x011NotRnIsPc(const NamedClassDecoder& decoder)
     : LoadStore2RegisterImm12OpTesterNotRnIsPc(decoder) {}
   virtual bool PassesParsePreconditions(
       nacl_arm_dec::Instruction inst,
       const NamedClassDecoder& decoder);
 
 };
@@ skipping 61 matching lines @@
   if ((inst.Bits() & 0x02000000) != 0x02000000 /* A(25:25) == ~1 */) return false;
   if ((inst.Bits() & 0x00500000) != 0x00100000 /* op1(24:20) == ~xx0x1 */) return false;
   if ((inst.Bits() & 0x00000010) != 0x00000000 /* B(4:4) == ~0 */) return false;
   if ((inst.Bits() & 0x01700000) == 0x00300000 /* op1_repeated(24:20) == 0x011 */) return false;
 
   // Check other preconditions defined for the base decoder.
   return LoadStore3RegisterImm5OpTester::
       PassesParsePreconditions(inst, decoder);
 }
 
+class UnsafeCondNopTesterA_25Is0_op1_24To20Is0x011
+    : public UnsafeCondNopTester {
+ public:
+  UnsafeCondNopTesterA_25Is0_op1_24To20Is0x011(const NamedClassDecoder& decoder)
+    : UnsafeCondNopTester(decoder) {}
+  virtual bool PassesParsePreconditions(
+      nacl_arm_dec::Instruction inst,
+      const NamedClassDecoder& decoder);
+
+};
+
+bool UnsafeCondNopTesterA_25Is0_op1_24To20Is0x011
+::PassesParsePreconditions(
+     nacl_arm_dec::Instruction inst,
+     const NamedClassDecoder& decoder) {
+
+  // Check that row patterns apply to pattern being checked.'
+  if ((inst.Bits() & 0x02000000) != 0x00000000 /* A(25:25) == ~0 */) return false;
+  if ((inst.Bits() & 0x01700000) != 0x00300000 /* op1(24:20) == ~0x011 */) return false;
+
+  // Check other preconditions defined for the base decoder.
+  return UnsafeCondNopTester::
+      PassesParsePreconditions(inst, decoder);
+}
+
+class UnsafeCondNopTesterA_25Is1_op1_24To20Is0x011_B_4Is0
+    : public UnsafeCondNopTester {
+ public:
+  UnsafeCondNopTesterA_25Is1_op1_24To20Is0x011_B_4Is0(const NamedClassDecoder& decoder)
+    : UnsafeCondNopTester(decoder) {}
+  virtual bool PassesParsePreconditions(
+      nacl_arm_dec::Instruction inst,
+      const NamedClassDecoder& decoder);
+
+};
+
+bool UnsafeCondNopTesterA_25Is1_op1_24To20Is0x011_B_4Is0
+::PassesParsePreconditions(
+     nacl_arm_dec::Instruction inst,
+     const NamedClassDecoder& decoder) {
+
+  // Check that row patterns apply to pattern being checked.'
+  if ((inst.Bits() & 0x02000000) != 0x02000000 /* A(25:25) == ~1 */) return false;
+  if ((inst.Bits() & 0x01700000) != 0x00300000 /* op1(24:20) == ~0x011 */) return false;
+  if ((inst.Bits() & 0x00000010) != 0x00000000 /* B(4:4) == ~0 */) return false;
+
+  // Check other preconditions defined for the base decoder.
+  return UnsafeCondNopTester::
+      PassesParsePreconditions(inst, decoder);
+}
+
 class LoadStore2RegisterImm12OpTesterA_25Is0_op1_24To20Isxx1x0_Notop1_repeated_24To20Is0x110
     : public LoadStore2RegisterImm12OpTester {
  public:
   LoadStore2RegisterImm12OpTesterA_25Is0_op1_24To20Isxx1x0_Notop1_repeated_24To20Is0x110(const NamedClassDecoder& decoder)
     : LoadStore2RegisterImm12OpTester(decoder) {}
   virtual bool PassesParsePreconditions(
       nacl_arm_dec::Instruction inst,
       const NamedClassDecoder& decoder);
 
 };
@@ skipping 33 matching lines @@
   if ((inst.Bits() & 0x02000000) != 0x02000000 /* A(25:25) == ~1 */) return false;
   if ((inst.Bits() & 0x00500000) != 0x00400000 /* op1(24:20) == ~xx1x0 */) return false;
   if ((inst.Bits() & 0x00000010) != 0x00000000 /* B(4:4) == ~0 */) return false;
   if ((inst.Bits() & 0x01700000) == 0x00600000 /* op1_repeated(24:20) == 0x110 */) return false;
 
   // Check other preconditions defined for the base decoder.
   return LoadStore3RegisterImm5OpTester::
       PassesParsePreconditions(inst, decoder);
 }
 
+class UnsafeCondNopTesterA_25Is0_op1_24To20Is0x110
+    : public UnsafeCondNopTester {
+ public:
+  UnsafeCondNopTesterA_25Is0_op1_24To20Is0x110(const NamedClassDecoder& decoder)
+    : UnsafeCondNopTester(decoder) {}
+  virtual bool PassesParsePreconditions(
+      nacl_arm_dec::Instruction inst,
+      const NamedClassDecoder& decoder);
+
+};
+
+bool UnsafeCondNopTesterA_25Is0_op1_24To20Is0x110
+::PassesParsePreconditions(
+     nacl_arm_dec::Instruction inst,
+     const NamedClassDecoder& decoder) {
+
+  // Check that row patterns apply to pattern being checked.'
+  if ((inst.Bits() & 0x02000000) != 0x00000000 /* A(25:25) == ~0 */) return false;
+  if ((inst.Bits() & 0x01700000) != 0x00600000 /* op1(24:20) == ~0x110 */) return false;
+
+  // Check other preconditions defined for the base decoder.
+  return UnsafeCondNopTester::
+      PassesParsePreconditions(inst, decoder);
+}
+
+class UnsafeCondNopTesterA_25Is1_op1_24To20Is0x110_B_4Is0
+    : public UnsafeCondNopTester {
+ public:
+  UnsafeCondNopTesterA_25Is1_op1_24To20Is0x110_B_4Is0(const NamedClassDecoder& decoder)
+    : UnsafeCondNopTester(decoder) {}
+  virtual bool PassesParsePreconditions(
+      nacl_arm_dec::Instruction inst,
+      const NamedClassDecoder& decoder);
+
+};
+
+bool UnsafeCondNopTesterA_25Is1_op1_24To20Is0x110_B_4Is0
+::PassesParsePreconditions(
+     nacl_arm_dec::Instruction inst,
+     const NamedClassDecoder& decoder) {
+
+  // Check that row patterns apply to pattern being checked.'
+  if ((inst.Bits() & 0x02000000) != 0x02000000 /* A(25:25) == ~1 */) return false;
+  if ((inst.Bits() & 0x01700000) != 0x00600000 /* op1(24:20) == ~0x110 */) return false;
+  if ((inst.Bits() & 0x00000010) != 0x00000000 /* B(4:4) == ~0 */) return false;
+
+  // Check other preconditions defined for the base decoder.
+  return UnsafeCondNopTester::
+      PassesParsePreconditions(inst, decoder);
+}
+
 class LoadStore2RegisterImm12OpTesterA_25Is0_op1_24To20Isxx1x1_NotRn_19To16Is1111_Notop1_repeated_24To20Is0x111NotRnIsPc
     : public LoadStore2RegisterImm12OpTesterNotRnIsPc {
  public:
   LoadStore2RegisterImm12OpTesterA_25Is0_op1_24To20Isxx1x1_NotRn_19To16Is1111_Notop1_repeated_24To20Is0x111NotRnIsPc(const NamedClassDecoder& decoder)
     : LoadStore2RegisterImm12OpTesterNotRnIsPc(decoder) {}
   virtual bool PassesParsePreconditions(
       nacl_arm_dec::Instruction inst,
       const NamedClassDecoder& decoder);
 
 };
@@ skipping 61 matching lines @@
   if ((inst.Bits() & 0x02000000) != 0x02000000 /* A(25:25) == ~1 */) return false;
   if ((inst.Bits() & 0x00500000) != 0x00500000 /* op1(24:20) == ~xx1x1 */) return false;
   if ((inst.Bits() & 0x00000010) != 0x00000000 /* B(4:4) == ~0 */) return false;
   if ((inst.Bits() & 0x01700000) == 0x00700000 /* op1_repeated(24:20) == 0x111 */) return false;
 
   // Check other preconditions defined for the base decoder.
   return LoadStore3RegisterImm5OpTester::
       PassesParsePreconditions(inst, decoder);
 }
 
+class UnsafeCondNopTesterA_25Is0_op1_24To20Is0x111
+    : public UnsafeCondNopTester {
+ public:
+  UnsafeCondNopTesterA_25Is0_op1_24To20Is0x111(const NamedClassDecoder& decoder)
+    : UnsafeCondNopTester(decoder) {}
+  virtual bool PassesParsePreconditions(
+      nacl_arm_dec::Instruction inst,
+      const NamedClassDecoder& decoder);
+
+};
+
+bool UnsafeCondNopTesterA_25Is0_op1_24To20Is0x111
+::PassesParsePreconditions(
+     nacl_arm_dec::Instruction inst,
+     const NamedClassDecoder& decoder) {
+
+  // Check that row patterns apply to pattern being checked.'
+  if ((inst.Bits() & 0x02000000) != 0x00000000 /* A(25:25) == ~0 */) return false;
+  if ((inst.Bits() & 0x01700000) != 0x00700000 /* op1(24:20) == ~0x111 */) return false;
+
+  // Check other preconditions defined for the base decoder.
+  return UnsafeCondNopTester::
+      PassesParsePreconditions(inst, decoder);
+}
+
+class UnsafeCondNopTesterA_25Is1_op1_24To20Is0x111_B_4Is0
+    : public UnsafeCondNopTester {
+ public:
+  UnsafeCondNopTesterA_25Is1_op1_24To20Is0x111_B_4Is0(const NamedClassDecoder& decoder)
+    : UnsafeCondNopTester(decoder) {}
+  virtual bool PassesParsePreconditions(
+      nacl_arm_dec::Instruction inst,
+      const NamedClassDecoder& decoder);
+
+};
+
+bool UnsafeCondNopTesterA_25Is1_op1_24To20Is0x111_B_4Is0
+::PassesParsePreconditions(
+     nacl_arm_dec::Instruction inst,
+     const NamedClassDecoder& decoder) {
+
+  // Check that row patterns apply to pattern being checked.'
+  if ((inst.Bits() & 0x02000000) != 0x02000000 /* A(25:25) == ~1 */) return false;
+  if ((inst.Bits() & 0x01700000) != 0x00700000 /* op1(24:20) == ~0x111 */) return false;
+  if ((inst.Bits() & 0x00000010) != 0x00000000 /* B(4:4) == ~0 */) return false;
+
+  // Check other preconditions defined for the base decoder.
+  return UnsafeCondNopTester::
+      PassesParsePreconditions(inst, decoder);
+}
+
 class LoadStore2RegisterImm12OpTesterFlags_24To21Is1001_Rn_19To16Is1101_Imm12_11To0Is000000000100
     : public LoadStore2RegisterImm12OpTester {
  public:
   LoadStore2RegisterImm12OpTesterFlags_24To21Is1001_Rn_19To16Is1101_Imm12_11To0Is000000000100(const NamedClassDecoder& decoder)
     : LoadStore2RegisterImm12OpTester(decoder) {}
   virtual bool PassesParsePreconditions(
       nacl_arm_dec::Instruction inst,
       const NamedClassDecoder& decoder);
 
 };
@@ skipping 184 matching lines @@
 
   // Check that row patterns apply to pattern being checked.'
   if ((inst.Bits() & 0x01E00000) != 0x01E00000 /* op1(24:20) == ~1111x */) return false;
   if ((inst.Bits() & 0x00000060) != 0x00000040 /* op2(7:5) == ~x10 */) return false;
 
   // Check other preconditions defined for the base decoder.
   return Binary2RegisterBitRangeNotRnIsPcTester::
       PassesParsePreconditions(inst, decoder);
 }
 
-class Unary1RegisterSetTesterop2_6To4Is000_op_22To21Isx0
+class UnsafeCondNopTesterop2_6To4Is000_B_9Is1_op_22To21Isx0
+    : public UnsafeCondNopTester {
+ public:
+  UnsafeCondNopTesterop2_6To4Is000_B_9Is1_op_22To21Isx0(const NamedClassDecoder& decoder)
+    : UnsafeCondNopTester(decoder) {}
+  virtual bool PassesParsePreconditions(
+      nacl_arm_dec::Instruction inst,
+      const NamedClassDecoder& decoder);
+
+};
+
+bool UnsafeCondNopTesterop2_6To4Is000_B_9Is1_op_22To21Isx0
+::PassesParsePreconditions(
+     nacl_arm_dec::Instruction inst,
+     const NamedClassDecoder& decoder) {
+
+  // Check that row patterns apply to pattern being checked.'
+  if ((inst.Bits() & 0x00000070) != 0x00000000 /* op2(6:4) == ~000 */) return false;
+  if ((inst.Bits() & 0x00000200) != 0x00000200 /* B(9:9) == ~1 */) return false;
+  if ((inst.Bits() & 0x00200000) != 0x00000000 /* op(22:21) == ~x0 */) return false;
+
+  // Check other preconditions defined for the base decoder.
+  return UnsafeCondNopTester::
+      PassesParsePreconditions(inst, decoder);
+}
+
+class UnsafeCondNopTesterop2_6To4Is000_B_9Is1_op_22To21Isx1
+    : public UnsafeCondNopTester {
+ public:
+  UnsafeCondNopTesterop2_6To4Is000_B_9Is1_op_22To21Isx1(const NamedClassDecoder& decoder)
+    : UnsafeCondNopTester(decoder) {}
+  virtual bool PassesParsePreconditions(
+      nacl_arm_dec::Instruction inst,
+      const NamedClassDecoder& decoder);
+
+};
+
+bool UnsafeCondNopTesterop2_6To4Is000_B_9Is1_op_22To21Isx1
+::PassesParsePreconditions(
+     nacl_arm_dec::Instruction inst,
+     const NamedClassDecoder& decoder) {
+
+  // Check that row patterns apply to pattern being checked.'
+  if ((inst.Bits() & 0x00000070) != 0x00000000 /* op2(6:4) == ~000 */) return false;
+  if ((inst.Bits() & 0x00000200) != 0x00000200 /* B(9:9) == ~1 */) return false;
+  if ((inst.Bits() & 0x00200000) != 0x00200000 /* op(22:21) == ~x1 */) return false;
+
+  // Check other preconditions defined for the base decoder.
+  return UnsafeCondNopTester::
+      PassesParsePreconditions(inst, decoder);
+}
+
+class Unary1RegisterSetTesterop2_6To4Is000_B_9Is0_op_22To21Isx0
     : public Unary1RegisterSetTester {
  public:
-  Unary1RegisterSetTesterop2_6To4Is000_op_22To21Isx0(const NamedClassDecoder& decoder)
+  Unary1RegisterSetTesterop2_6To4Is000_B_9Is0_op_22To21Isx0(const NamedClassDecoder& decoder)
     : Unary1RegisterSetTester(decoder) {}
   virtual bool PassesParsePreconditions(
       nacl_arm_dec::Instruction inst,
       const NamedClassDecoder& decoder);
 
 };
 
-bool Unary1RegisterSetTesterop2_6To4Is000_op_22To21Isx0
+bool Unary1RegisterSetTesterop2_6To4Is000_B_9Is0_op_22To21Isx0
 ::PassesParsePreconditions(
      nacl_arm_dec::Instruction inst,
      const NamedClassDecoder& decoder) {
 
   // Check that row patterns apply to pattern being checked.'
   if ((inst.Bits() & 0x00000070) != 0x00000000 /* op2(6:4) == ~000 */) return false;
+  if ((inst.Bits() & 0x00000200) != 0x00000000 /* B(9:9) == ~0 */) return false;
   if ((inst.Bits() & 0x00200000) != 0x00000000 /* op(22:21) == ~x0 */) return false;
 
   // Check other preconditions defined for the base decoder.
   return Unary1RegisterSetTester::
       PassesParsePreconditions(inst, decoder);
 }
 
-class Unary1RegisterUseTesterop2_6To4Is000_op_22To21Is01_op1_19To16Isxx00
+class Unary1RegisterUseTesterop2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx00
     : public Unary1RegisterUseTester {
  public:
-  Unary1RegisterUseTesterop2_6To4Is000_op_22To21Is01_op1_19To16Isxx00(const NamedClassDecoder& decoder)
+  Unary1RegisterUseTesterop2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx00(const NamedClassDecoder& decoder)
     : Unary1RegisterUseTester(decoder) {}
   virtual bool PassesParsePreconditions(
       nacl_arm_dec::Instruction inst,
       const NamedClassDecoder& decoder);
 
 };
 
-bool Unary1RegisterUseTesterop2_6To4Is000_op_22To21Is01_op1_19To16Isxx00
+bool Unary1RegisterUseTesterop2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx00
 ::PassesParsePreconditions(
      nacl_arm_dec::Instruction inst,
      const NamedClassDecoder& decoder) {
 
   // Check that row patterns apply to pattern being checked.'
   if ((inst.Bits() & 0x00000070) != 0x00000000 /* op2(6:4) == ~000 */) return false;
+  if ((inst.Bits() & 0x00000200) != 0x00000000 /* B(9:9) == ~0 */) return false;
   if ((inst.Bits() & 0x00600000) != 0x00200000 /* op(22:21) == ~01 */) return false;
   if ((inst.Bits() & 0x00030000) != 0x00000000 /* op1(19:16) == ~xx00 */) return false;
 
   // Check other preconditions defined for the base decoder.
   return Unary1RegisterUseTester::
       PassesParsePreconditions(inst, decoder);
 }
 
-class UnsafeCondNopTesterop2_6To4Is000_op_22To21Is01_op1_19To16Isxx01
+class UnsafeCondNopTesterop2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx01
     : public UnsafeCondNopTester {
  public:
-  UnsafeCondNopTesterop2_6To4Is000_op_22To21Is01_op1_19To16Isxx01(const NamedClassDecoder& decoder)
+  UnsafeCondNopTesterop2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx01(const NamedClassDecoder& decoder)
     : UnsafeCondNopTester(decoder) {}
   virtual bool PassesParsePreconditions(
       nacl_arm_dec::Instruction inst,
       const NamedClassDecoder& decoder);
 
 };
 
-bool UnsafeCondNopTesterop2_6To4Is000_op_22To21Is01_op1_19To16Isxx01
+bool UnsafeCondNopTesterop2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx01
 ::PassesParsePreconditions(
      nacl_arm_dec::Instruction inst,
      const NamedClassDecoder& decoder) {
 
   // Check that row patterns apply to pattern being checked.'
   if ((inst.Bits() & 0x00000070) != 0x00000000 /* op2(6:4) == ~000 */) return false;
+  if ((inst.Bits() & 0x00000200) != 0x00000000 /* B(9:9) == ~0 */) return false;
   if ((inst.Bits() & 0x00600000) != 0x00200000 /* op(22:21) == ~01 */) return false;
   if ((inst.Bits() & 0x00030000) != 0x00010000 /* op1(19:16) == ~xx01 */) return false;
 
   // Check other preconditions defined for the base decoder.
   return UnsafeCondNopTester::
       PassesParsePreconditions(inst, decoder);
 }
 
-class UnsafeCondNopTesterop2_6To4Is000_op_22To21Is01_op1_19To16Isxx1x
+class UnsafeCondNopTesterop2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx1x
     : public UnsafeCondNopTester {
  public:
-  UnsafeCondNopTesterop2_6To4Is000_op_22To21Is01_op1_19To16Isxx1x(const NamedClassDecoder& decoder)
+  UnsafeCondNopTesterop2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx1x(const NamedClassDecoder& decoder)
     : UnsafeCondNopTester(decoder) {}
   virtual bool PassesParsePreconditions(
       nacl_arm_dec::Instruction inst,
       const NamedClassDecoder& decoder);
 
 };
 
-bool UnsafeCondNopTesterop2_6To4Is000_op_22To21Is01_op1_19To16Isxx1x
+bool UnsafeCondNopTesterop2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx1x
 ::PassesParsePreconditions(
      nacl_arm_dec::Instruction inst,
      const NamedClassDecoder& decoder) {
 
   // Check that row patterns apply to pattern being checked.'
   if ((inst.Bits() & 0x00000070) != 0x00000000 /* op2(6:4) == ~000 */) return false;
+  if ((inst.Bits() & 0x00000200) != 0x00000000 /* B(9:9) == ~0 */) return false;
   if ((inst.Bits() & 0x00600000) != 0x00200000 /* op(22:21) == ~01 */) return false;
   if ((inst.Bits() & 0x00020000) != 0x00020000 /* op1(19:16) == ~xx1x */) return false;
 
   // Check other preconditions defined for the base decoder.
   return UnsafeCondNopTester::
       PassesParsePreconditions(inst, decoder);
 }
 
-class UnsafeCondNopTesterop2_6To4Is000_op_22To21Is11
+class UnsafeCondNopTesterop2_6To4Is000_B_9Is0_op_22To21Is11
     : public UnsafeCondNopTester {
  public:
-  UnsafeCondNopTesterop2_6To4Is000_op_22To21Is11(const NamedClassDecoder& decoder)
+  UnsafeCondNopTesterop2_6To4Is000_B_9Is0_op_22To21Is11(const NamedClassDecoder& decoder)
     : UnsafeCondNopTester(decoder) {}
   virtual bool PassesParsePreconditions(
       nacl_arm_dec::Instruction inst,
       const NamedClassDecoder& decoder);
 
 };
 
-bool UnsafeCondNopTesterop2_6To4Is000_op_22To21Is11
+bool UnsafeCondNopTesterop2_6To4Is000_B_9Is0_op_22To21Is11
 ::PassesParsePreconditions(
      nacl_arm_dec::Instruction inst,
      const NamedClassDecoder& decoder) {
 
   // Check that row patterns apply to pattern being checked.'
   if ((inst.Bits() & 0x00000070) != 0x00000000 /* op2(6:4) == ~000 */) return false;
+  if ((inst.Bits() & 0x00000200) != 0x00000000 /* B(9:9) == ~0 */) return false;
   if ((inst.Bits() & 0x00600000) != 0x00600000 /* op(22:21) == ~11 */) return false;
 
   // Check other preconditions defined for the base decoder.
   return UnsafeCondNopTester::
       PassesParsePreconditions(inst, decoder);
 }
 
 class BranchToRegisterTesterop2_6To4Is001_op_22To21Is01
     : public BranchToRegisterTester {
  public:
@@ skipping 87 matching lines @@
 
   // Check that row patterns apply to pattern being checked.'
   if ((inst.Bits() & 0x00000070) != 0x00000030 /* op2(6:4) == ~011 */) return false;
   if ((inst.Bits() & 0x00600000) != 0x00200000 /* op(22:21) == ~01 */) return false;
 
   // Check other preconditions defined for the base decoder.
   return BranchToRegisterTesterRegsNotPc::
       PassesParsePreconditions(inst, decoder);
 }
 
+class UnsafeCondNopTesterop2_6To4Is110_op_22To21Is11
+    : public UnsafeCondNopTester {
+ public:
+  UnsafeCondNopTesterop2_6To4Is110_op_22To21Is11(const NamedClassDecoder& decoder)
+    : UnsafeCondNopTester(decoder) {}
+  virtual bool PassesParsePreconditions(
+      nacl_arm_dec::Instruction inst,
+      const NamedClassDecoder& decoder);
+
+};
+
+bool UnsafeCondNopTesterop2_6To4Is110_op_22To21Is11
+::PassesParsePreconditions(
+     nacl_arm_dec::Instruction inst,
+     const NamedClassDecoder& decoder) {
+
+  // Check that row patterns apply to pattern being checked.'
+  if ((inst.Bits() & 0x00000070) != 0x00000060 /* op2(6:4) == ~110 */) return false;
+  if ((inst.Bits() & 0x00600000) != 0x00600000 /* op(22:21) == ~11 */) return false;
+
+  // Check other preconditions defined for the base decoder.
+  return UnsafeCondNopTester::
+      PassesParsePreconditions(inst, decoder);
+}
+
 class Immediate16UseTesterop2_6To4Is111_op_22To21Is01
     : public Immediate16UseTester {
  public:
   Immediate16UseTesterop2_6To4Is111_op_22To21Is01(const NamedClassDecoder& decoder)
     : Immediate16UseTester(decoder) {}
   virtual bool PassesParsePreconditions(
       nacl_arm_dec::Instruction inst,
       const NamedClassDecoder& decoder);
 
 };
 
 bool Immediate16UseTesterop2_6To4Is111_op_22To21Is01
 ::PassesParsePreconditions(
      nacl_arm_dec::Instruction inst,
      const NamedClassDecoder& decoder) {
 
   // Check that row patterns apply to pattern being checked.'
   if ((inst.Bits() & 0x00000070) != 0x00000070 /* op2(6:4) == ~111 */) return false;
   if ((inst.Bits() & 0x00600000) != 0x00200000 /* op(22:21) == ~01 */) return false;
 
   // Check other preconditions defined for the base decoder.
   return Immediate16UseTester::
       PassesParsePreconditions(inst, decoder);
 }
 
+class UnsafeCondNopTesterop2_6To4Is111_op_22To21Is10
+    : public UnsafeCondNopTester {
+ public:
+  UnsafeCondNopTesterop2_6To4Is111_op_22To21Is10(const NamedClassDecoder& decoder)
+    : UnsafeCondNopTester(decoder) {}
+  virtual bool PassesParsePreconditions(
+      nacl_arm_dec::Instruction inst,
+      const NamedClassDecoder& decoder);
+
+};
+
+bool UnsafeCondNopTesterop2_6To4Is111_op_22To21Is10
+::PassesParsePreconditions(
+     nacl_arm_dec::Instruction inst,
+     const NamedClassDecoder& decoder) {
+
+  // Check that row patterns apply to pattern being checked.'
+  if ((inst.Bits() & 0x00000070) != 0x00000070 /* op2(6:4) == ~111 */) return false;
+  if ((inst.Bits() & 0x00600000) != 0x00400000 /* op(22:21) == ~10 */) return false;
+
+  // Check other preconditions defined for the base decoder.
+  return UnsafeCondNopTester::
+      PassesParsePreconditions(inst, decoder);
+}
+
 class UnsafeCondNopTesterop2_6To4Is111_op_22To21Is11
     : public UnsafeCondNopTester {
  public:
   UnsafeCondNopTesterop2_6To4Is111_op_22To21Is11(const NamedClassDecoder& decoder)
     : UnsafeCondNopTester(decoder) {}
   virtual bool PassesParsePreconditions(
       nacl_arm_dec::Instruction inst,
       const NamedClassDecoder& decoder);
 
 };
@@ skipping 161 matching lines @@
   // Check that row patterns apply to pattern being checked.'
   if ((inst.Bits() & 0x00400000) != 0x00000000 /* op(22:22) == ~0 */) return false;
   if ((inst.Bits() & 0x000F0000) != 0x00000000 /* op1(19:16) == ~0000 */) return false;
   if ((inst.Bits() & 0x000000F0) != 0x000000F0 /* op2(7:0) == ~1111xxxx */) return false;
 
   // Check other preconditions defined for the base decoder.
   return CondNopTester::
       PassesParsePreconditions(inst, decoder);
 }
 
+class MoveImmediate12ToApsrTesterop_22Is0_op1_19To16Is0100
+    : public MoveImmediate12ToApsrTester {
+ public:
+  MoveImmediate12ToApsrTesterop_22Is0_op1_19To16Is0100(const NamedClassDecoder& decoder)
+    : MoveImmediate12ToApsrTester(decoder) {}
+  virtual bool PassesParsePreconditions(
+      nacl_arm_dec::Instruction inst,
+      const NamedClassDecoder& decoder);
+
+};
+
+bool MoveImmediate12ToApsrTesterop_22Is0_op1_19To16Is0100
+::PassesParsePreconditions(
+     nacl_arm_dec::Instruction inst,
+     const NamedClassDecoder& decoder) {
+
+  // Check that row patterns apply to pattern being checked.'
+  if ((inst.Bits() & 0x00400000) != 0x00000000 /* op(22:22) == ~0 */) return false;
+  if ((inst.Bits() & 0x000F0000) != 0x00040000 /* op1(19:16) == ~0100 */) return false;
+
+  // Check other preconditions defined for the base decoder.
+  return MoveImmediate12ToApsrTester::
+      PassesParsePreconditions(inst, decoder);
+}
+
+class MoveImmediate12ToApsrTesterop_22Is0_op1_19To16Is1x00
+    : public MoveImmediate12ToApsrTester {
+ public:
+  MoveImmediate12ToApsrTesterop_22Is0_op1_19To16Is1x00(const NamedClassDecoder& decoder)
+    : MoveImmediate12ToApsrTester(decoder) {}
+  virtual bool PassesParsePreconditions(
+      nacl_arm_dec::Instruction inst,
+      const NamedClassDecoder& decoder);
+
+};
+
+bool MoveImmediate12ToApsrTesterop_22Is0_op1_19To16Is1x00
+::PassesParsePreconditions(
+     nacl_arm_dec::Instruction inst,
+     const NamedClassDecoder& decoder) {
+
+  // Check that row patterns apply to pattern being checked.'
+  if ((inst.Bits() & 0x00400000) != 0x00000000 /* op(22:22) == ~0 */) return false;
+  if ((inst.Bits() & 0x000B0000) != 0x00080000 /* op1(19:16) == ~1x00 */) return false;
+
+  // Check other preconditions defined for the base decoder.
+  return MoveImmediate12ToApsrTester::
+      PassesParsePreconditions(inst, decoder);
+}
+
 class UnsafeCondNopTesterop_22Is0_op1_19To16Isxx01
     : public UnsafeCondNopTester {
  public:
   UnsafeCondNopTesterop_22Is0_op1_19To16Isxx01(const NamedClassDecoder& decoder)
     : UnsafeCondNopTester(decoder) {}
   virtual bool PassesParsePreconditions(
       nacl_arm_dec::Instruction inst,
       const NamedClassDecoder& decoder);
 
 };
@@ skipping 1884 matching lines @@
 
   // Check that row patterns apply to pattern being checked.'
   if ((inst.Bits() & 0x00700000) != 0x00500000 /* op1(22:20) == ~101 */) return false;
   if ((inst.Bits() & 0x000000C0) != 0x000000C0 /* op2(7:5) == ~11x */) return false;
 
   // Check other preconditions defined for the base decoder.
   return Binary4RegisterDualOpTesterRegsNotPc::
       PassesParsePreconditions(inst, decoder);
 }
 
+class UnsafeCondNopTesterop_23To20Is0x00
+    : public UnsafeCondNopTester {
+ public:
+  UnsafeCondNopTesterop_23To20Is0x00(const NamedClassDecoder& decoder)
+    : UnsafeCondNopTester(decoder) {}
+  virtual bool PassesParsePreconditions(
+      nacl_arm_dec::Instruction inst,
+      const NamedClassDecoder& decoder);
+
+};
+
+bool UnsafeCondNopTesterop_23To20Is0x00
+::PassesParsePreconditions(
+     nacl_arm_dec::Instruction inst,
+     const NamedClassDecoder& decoder) {
+
+  // Check that row patterns apply to pattern being checked.'
+  if ((inst.Bits() & 0x00B00000) != 0x00000000 /* op(23:20) == ~0x00 */) return false;
+
+  // Check other preconditions defined for the base decoder.
+  return UnsafeCondNopTester::
+      PassesParsePreconditions(inst, decoder);
+}
+
 class StoreExclusive3RegisterOpTesterop_23To20Is1000
     : public StoreExclusive3RegisterOpTester {
  public:
   StoreExclusive3RegisterOpTesterop_23To20Is1000(const NamedClassDecoder& decoder)
     : StoreExclusive3RegisterOpTester(decoder) {}
   virtual bool PassesParsePreconditions(
       nacl_arm_dec::Instruction inst,
       const NamedClassDecoder& decoder);
 
 };
@@ skipping 500 matching lines @@
 
 class BranchImmediate24Tester_op_25To20Is11xxxx_Bl_Blx_Rule_23_A1_P58
     : public BranchImmediate24Testerop_25To20Is11xxxx {
  public:
   BranchImmediate24Tester_op_25To20Is11xxxx_Bl_Blx_Rule_23_A1_P58()
     : BranchImmediate24Testerop_25To20Is11xxxx(
       state_.BranchImmediate24_Bl_Blx_Rule_23_A1_P58_instance_)
   {}
 };
 
+class ForbiddenCondNopTester_op_25Is0_op1_24To20Is0xx1x_op2_7To4Is1011_extra_load_store_instructions_unpriviledged
+    : public UnsafeCondNopTesterop_25Is0_op1_24To20Is0xx1x_op2_7To4Is1011 {
+ public:
+  ForbiddenCondNopTester_op_25Is0_op1_24To20Is0xx1x_op2_7To4Is1011_extra_load_store_instructions_unpriviledged()
+    : UnsafeCondNopTesterop_25Is0_op1_24To20Is0xx1x_op2_7To4Is1011(
+      state_.ForbiddenCondNop_extra_load_store_instructions_unpriviledged_instance_)
+  {}
+};
+
+class ForbiddenCondNopTester_op_25Is0_op1_24To20Is0xx1x_op2_7To4Is11x1_extra_load_store_instructions_unpriviledged
+    : public UnsafeCondNopTesterop_25Is0_op1_24To20Is0xx1x_op2_7To4Is11x1 {
+ public:
+  ForbiddenCondNopTester_op_25Is0_op1_24To20Is0xx1x_op2_7To4Is11x1_extra_load_store_instructions_unpriviledged()
+    : UnsafeCondNopTesterop_25Is0_op1_24To20Is0xx1x_op2_7To4Is11x1(
+      state_.ForbiddenCondNop_extra_load_store_instructions_unpriviledged_instance_)
+  {}
+};
+
 class Unary1RegisterImmediateOpTester_op_25Is1_op1_24To20Is10000RegsNotPc_Mov_Rule_96_A2_P194
     : public Unary1RegisterImmediateOpTesterop_25Is1_op1_24To20Is10000RegsNotPc {
  public:
   Unary1RegisterImmediateOpTester_op_25Is1_op1_24To20Is10000RegsNotPc_Mov_Rule_96_A2_P194()
     : Unary1RegisterImmediateOpTesterop_25Is1_op1_24To20Is10000RegsNotPc(
       state_.Unary1RegisterImmediateOp_Mov_Rule_96_A2_P194_instance_)
   {}
 };
 
 class Unary1RegisterImmediateOpTester_op_25Is1_op1_24To20Is10100RegsNotPc_Mov_Rule_99_A1_P200
@@ skipping 34 matching lines @@
 
 class Unary1RegisterImmediateOpTester_op_24To20Is00100_Rn_19To16Is1111_Adr_Rule_10_A2_P32
     : public Unary1RegisterImmediateOpTesterop_24To20Is00100_Rn_19To16Is1111 {
  public:
   Unary1RegisterImmediateOpTester_op_24To20Is00100_Rn_19To16Is1111_Adr_Rule_10_A2_P32()
     : Unary1RegisterImmediateOpTesterop_24To20Is00100_Rn_19To16Is1111(
       state_.Unary1RegisterImmediateOp_Adr_Rule_10_A2_P32_instance_)
   {}
 };
 
+class ForbiddenCondNopTester_op_24To20Is00101_Rn_19To16Is1111_Subs_Pc_Lr_and_related_instructions_Rule_A1a
+    : public UnsafeCondNopTesterop_24To20Is00101_Rn_19To16Is1111 {
+ public:
+  ForbiddenCondNopTester_op_24To20Is00101_Rn_19To16Is1111_Subs_Pc_Lr_and_related_instructions_Rule_A1a()
+    : UnsafeCondNopTesterop_24To20Is00101_Rn_19To16Is1111(
+      state_.ForbiddenCondNop_Subs_Pc_Lr_and_related_instructions_Rule_A1a_instance_)
+  {}
+};
+
 class Binary2RegisterImmediateOpTester_op_24To20Is0011xNotRdIsPcAndS_Rsb_Rule_142_A1_P284
     : public Binary2RegisterImmediateOpTesterop_24To20Is0011xNotRdIsPcAndS {
  public:
   Binary2RegisterImmediateOpTester_op_24To20Is0011xNotRdIsPcAndS_Rsb_Rule_142_A1_P284()
     : Binary2RegisterImmediateOpTesterop_24To20Is0011xNotRdIsPcAndS(
       state_.Binary2RegisterImmediateOp_Rsb_Rule_142_A1_P284_instance_)
   {}
 };
 
 class Binary2RegisterImmediateOpTester_op_24To20Is0100x_NotRn_19To16Is1111NeitherRdIsPcAndSNorRnIsPcAndNotS_Add_Rule_5_A1_P22
     : public Binary2RegisterImmediateOpTesterop_24To20Is0100x_NotRn_19To16Is1111NeitherRdIsPcAndSNorRnIsPcAndNotS {
  public:
   Binary2RegisterImmediateOpTester_op_24To20Is0100x_NotRn_19To16Is1111NeitherRdIsPcAndSNorRnIsPcAndNotS_Add_Rule_5_A1_P22()
     : Binary2RegisterImmediateOpTesterop_24To20Is0100x_NotRn_19To16Is1111NeitherRdIsPcAndSNorRnIsPcAndNotS(
       state_.Binary2RegisterImmediateOp_Add_Rule_5_A1_P22_instance_)
   {}
 };
 
 class Unary1RegisterImmediateOpTester_op_24To20Is01000_Rn_19To16Is1111_Adr_Rule_10_A1_P32
     : public Unary1RegisterImmediateOpTesterop_24To20Is01000_Rn_19To16Is1111 {
  public:
   Unary1RegisterImmediateOpTester_op_24To20Is01000_Rn_19To16Is1111_Adr_Rule_10_A1_P32()
     : Unary1RegisterImmediateOpTesterop_24To20Is01000_Rn_19To16Is1111(
       state_.Unary1RegisterImmediateOp_Adr_Rule_10_A1_P32_instance_)
   {}
 };
 
+class ForbiddenCondNopTester_op_24To20Is01001_Rn_19To16Is1111_Subs_Pc_Lr_and_related_instructions_Rule_A1b
+    : public UnsafeCondNopTesterop_24To20Is01001_Rn_19To16Is1111 {
+ public:
+  ForbiddenCondNopTester_op_24To20Is01001_Rn_19To16Is1111_Subs_Pc_Lr_and_related_instructions_Rule_A1b()
+    : UnsafeCondNopTesterop_24To20Is01001_Rn_19To16Is1111(
+      state_.ForbiddenCondNop_Subs_Pc_Lr_and_related_instructions_Rule_A1b_instance_)
+  {}
+};
+
 class Binary2RegisterImmediateOpTester_op_24To20Is0101xNotRdIsPcAndS_Adc_Rule_6_A1_P14
     : public Binary2RegisterImmediateOpTesterop_24To20Is0101xNotRdIsPcAndS {
  public:
   Binary2RegisterImmediateOpTester_op_24To20Is0101xNotRdIsPcAndS_Adc_Rule_6_A1_P14()
     : Binary2RegisterImmediateOpTesterop_24To20Is0101xNotRdIsPcAndS(
       state_.Binary2RegisterImmediateOp_Adc_Rule_6_A1_P14_instance_)
   {}
 };
 
 class Binary2RegisterImmediateOpTester_op_24To20Is0110xNotRdIsPcAndS_Sbc_Rule_151_A1_P302
@@ skipping 790 matching lines @@
 
 class Store3RegisterImm5OpTester_A_25Is1_op1_24To20Isxx0x0_B_4Is0_Notop1_repeated_24To20Is0x010_Str_Rule_195_A1_P386
     : public LoadStore3RegisterImm5OpTesterA_25Is1_op1_24To20Isxx0x0_B_4Is0_Notop1_repeated_24To20Is0x010 {
  public:
   Store3RegisterImm5OpTester_A_25Is1_op1_24To20Isxx0x0_B_4Is0_Notop1_repeated_24To20Is0x010_Str_Rule_195_A1_P386()
     : LoadStore3RegisterImm5OpTesterA_25Is1_op1_24To20Isxx0x0_B_4Is0_Notop1_repeated_24To20Is0x010(
       state_.Store3RegisterImm5Op_Str_Rule_195_A1_P386_instance_)
   {}
 };
 
+class ForbiddenCondNopTester_A_25Is0_op1_24To20Is0x010_Strt_Rule_A1
+    : public UnsafeCondNopTesterA_25Is0_op1_24To20Is0x010 {
+ public:
+  ForbiddenCondNopTester_A_25Is0_op1_24To20Is0x010_Strt_Rule_A1()
+    : UnsafeCondNopTesterA_25Is0_op1_24To20Is0x010(
+      state_.ForbiddenCondNop_Strt_Rule_A1_instance_)
+  {}
+};
+
+class ForbiddenCondNopTester_A_25Is1_op1_24To20Is0x010_B_4Is0_Strt_Rule_A2
+    : public UnsafeCondNopTesterA_25Is1_op1_24To20Is0x010_B_4Is0 {
+ public:
+  ForbiddenCondNopTester_A_25Is1_op1_24To20Is0x010_B_4Is0_Strt_Rule_A2()
+    : UnsafeCondNopTesterA_25Is1_op1_24To20Is0x010_B_4Is0(
+      state_.ForbiddenCondNop_Strt_Rule_A2_instance_)
+  {}
+};
+
 class Load2RegisterImm12OpTester_A_25Is0_op1_24To20Isxx0x1_NotRn_19To16Is1111_Notop1_repeated_24To20Is0x011NotRnIsPc_Ldr_Rule_58_A1_P120
     : public LoadStore2RegisterImm12OpTesterA_25Is0_op1_24To20Isxx0x1_NotRn_19To16Is1111_Notop1_repeated_24To20Is0x011NotRnIsPc {
  public:
   Load2RegisterImm12OpTester_A_25Is0_op1_24To20Isxx0x1_NotRn_19To16Is1111_Notop1_repeated_24To20Is0x011NotRnIsPc_Ldr_Rule_58_A1_P120()
     : LoadStore2RegisterImm12OpTesterA_25Is0_op1_24To20Isxx0x1_NotRn_19To16Is1111_Notop1_repeated_24To20Is0x011NotRnIsPc(
       state_.Load2RegisterImm12Op_Ldr_Rule_58_A1_P120_instance_)
   {}
 };
 
 class Load2RegisterImm12OpTester_A_25Is0_op1_24To20Isxx0x1_Rn_19To16Is1111_Notop1_repeated_24To20Is0x011_Ldr_Rule_59_A1_P122
     : public LoadStore2RegisterImm12OpTesterA_25Is0_op1_24To20Isxx0x1_Rn_19To16Is1111_Notop1_repeated_24To20Is0x011 {
  public:
   Load2RegisterImm12OpTester_A_25Is0_op1_24To20Isxx0x1_Rn_19To16Is1111_Notop1_repeated_24To20Is0x011_Ldr_Rule_59_A1_P122()
     : LoadStore2RegisterImm12OpTesterA_25Is0_op1_24To20Isxx0x1_Rn_19To16Is1111_Notop1_repeated_24To20Is0x011(
       state_.Load2RegisterImm12Op_Ldr_Rule_59_A1_P122_instance_)
   {}
 };
 
 class Load3RegisterImm5OpTester_A_25Is1_op1_24To20Isxx0x1_B_4Is0_Notop1_repeated_24To20Is0x011_Ldr_Rule_60_A1_P124
     : public LoadStore3RegisterImm5OpTesterA_25Is1_op1_24To20Isxx0x1_B_4Is0_Notop1_repeated_24To20Is0x011 {
  public:
   Load3RegisterImm5OpTester_A_25Is1_op1_24To20Isxx0x1_B_4Is0_Notop1_repeated_24To20Is0x011_Ldr_Rule_60_A1_P124()
     : LoadStore3RegisterImm5OpTesterA_25Is1_op1_24To20Isxx0x1_B_4Is0_Notop1_repeated_24To20Is0x011(
       state_.Load3RegisterImm5Op_Ldr_Rule_60_A1_P124_instance_)
   {}
 };
 
+class ForbiddenCondNopTester_A_25Is0_op1_24To20Is0x011_Ldrt_Rule_A1
+    : public UnsafeCondNopTesterA_25Is0_op1_24To20Is0x011 {
+ public:
+  ForbiddenCondNopTester_A_25Is0_op1_24To20Is0x011_Ldrt_Rule_A1()
+    : UnsafeCondNopTesterA_25Is0_op1_24To20Is0x011(
+      state_.ForbiddenCondNop_Ldrt_Rule_A1_instance_)
+  {}
+};
+
+class ForbiddenCondNopTester_A_25Is1_op1_24To20Is0x011_B_4Is0_Ldrt_Rule_A2
+    : public UnsafeCondNopTesterA_25Is1_op1_24To20Is0x011_B_4Is0 {
+ public:
+  ForbiddenCondNopTester_A_25Is1_op1_24To20Is0x011_B_4Is0_Ldrt_Rule_A2()
+    : UnsafeCondNopTesterA_25Is1_op1_24To20Is0x011_B_4Is0(
+      state_.ForbiddenCondNop_Ldrt_Rule_A2_instance_)
+  {}
+};
+
 class Store2RegisterImm12OpTester_A_25Is0_op1_24To20Isxx1x0_Notop1_repeated_24To20Is0x110_Strb_Rule_197_A1_P390
     : public LoadStore2RegisterImm12OpTesterA_25Is0_op1_24To20Isxx1x0_Notop1_repeated_24To20Is0x110 {
  public:
   Store2RegisterImm12OpTester_A_25Is0_op1_24To20Isxx1x0_Notop1_repeated_24To20Is0x110_Strb_Rule_197_A1_P390()
     : LoadStore2RegisterImm12OpTesterA_25Is0_op1_24To20Isxx1x0_Notop1_repeated_24To20Is0x110(
       state_.Store2RegisterImm12Op_Strb_Rule_197_A1_P390_instance_)
   {}
 };
 
 class Store3RegisterImm5OpTester_A_25Is1_op1_24To20Isxx1x0_B_4Is0_Notop1_repeated_24To20Is0x110_Strb_Rule_198_A1_P392
     : public LoadStore3RegisterImm5OpTesterA_25Is1_op1_24To20Isxx1x0_B_4Is0_Notop1_repeated_24To20Is0x110 {
  public:
   Store3RegisterImm5OpTester_A_25Is1_op1_24To20Isxx1x0_B_4Is0_Notop1_repeated_24To20Is0x110_Strb_Rule_198_A1_P392()
     : LoadStore3RegisterImm5OpTesterA_25Is1_op1_24To20Isxx1x0_B_4Is0_Notop1_repeated_24To20Is0x110(
       state_.Store3RegisterImm5Op_Strb_Rule_198_A1_P392_instance_)
   {}
 };
 
+class ForbiddenCondNopTester_A_25Is0_op1_24To20Is0x110_Strtb_Rule_A1
+    : public UnsafeCondNopTesterA_25Is0_op1_24To20Is0x110 {
+ public:
+  ForbiddenCondNopTester_A_25Is0_op1_24To20Is0x110_Strtb_Rule_A1()
+    : UnsafeCondNopTesterA_25Is0_op1_24To20Is0x110(
+      state_.ForbiddenCondNop_Strtb_Rule_A1_instance_)
+  {}
+};
+
+class ForbiddenCondNopTester_A_25Is1_op1_24To20Is0x110_B_4Is0_Strtb_Rule_A2
+    : public UnsafeCondNopTesterA_25Is1_op1_24To20Is0x110_B_4Is0 {
+ public:
+  ForbiddenCondNopTester_A_25Is1_op1_24To20Is0x110_B_4Is0_Strtb_Rule_A2()
+    : UnsafeCondNopTesterA_25Is1_op1_24To20Is0x110_B_4Is0(
+      state_.ForbiddenCondNop_Strtb_Rule_A2_instance_)
+  {}
+};
+
 class Load2RegisterImm12OpTester_A_25Is0_op1_24To20Isxx1x1_NotRn_19To16Is1111_Notop1_repeated_24To20Is0x111NotRnIsPc_Ldrb_Rule_62_A1_P128
     : public LoadStore2RegisterImm12OpTesterA_25Is0_op1_24To20Isxx1x1_NotRn_19To16Is1111_Notop1_repeated_24To20Is0x111NotRnIsPc {
  public:
   Load2RegisterImm12OpTester_A_25Is0_op1_24To20Isxx1x1_NotRn_19To16Is1111_Notop1_repeated_24To20Is0x111NotRnIsPc_Ldrb_Rule_62_A1_P128()
     : LoadStore2RegisterImm12OpTesterA_25Is0_op1_24To20Isxx1x1_NotRn_19To16Is1111_Notop1_repeated_24To20Is0x111NotRnIsPc(
       state_.Load2RegisterImm12Op_Ldrb_Rule_62_A1_P128_instance_)
   {}
 };
 
 class Load2RegisterImm12OpTester_A_25Is0_op1_24To20Isxx1x1_Rn_19To16Is1111_Notop1_repeated_24To20Is0x111_Ldrb_Rule_63_A1_P130
     : public LoadStore2RegisterImm12OpTesterA_25Is0_op1_24To20Isxx1x1_Rn_19To16Is1111_Notop1_repeated_24To20Is0x111 {
  public:
   Load2RegisterImm12OpTester_A_25Is0_op1_24To20Isxx1x1_Rn_19To16Is1111_Notop1_repeated_24To20Is0x111_Ldrb_Rule_63_A1_P130()
     : LoadStore2RegisterImm12OpTesterA_25Is0_op1_24To20Isxx1x1_Rn_19To16Is1111_Notop1_repeated_24To20Is0x111(
       state_.Load2RegisterImm12Op_Ldrb_Rule_63_A1_P130_instance_)
   {}
 };
 
 class Load3RegisterImm5OpTester_A_25Is1_op1_24To20Isxx1x1_B_4Is0_Notop1_repeated_24To20Is0x111_Ldrb_Rule_64_A1_P132
     : public LoadStore3RegisterImm5OpTesterA_25Is1_op1_24To20Isxx1x1_B_4Is0_Notop1_repeated_24To20Is0x111 {
  public:
   Load3RegisterImm5OpTester_A_25Is1_op1_24To20Isxx1x1_B_4Is0_Notop1_repeated_24To20Is0x111_Ldrb_Rule_64_A1_P132()
     : LoadStore3RegisterImm5OpTesterA_25Is1_op1_24To20Isxx1x1_B_4Is0_Notop1_repeated_24To20Is0x111(
       state_.Load3RegisterImm5Op_Ldrb_Rule_64_A1_P132_instance_)
   {}
 };
 
+class ForbiddenCondNopTester_A_25Is0_op1_24To20Is0x111_Ldrtb_Rule_A1
+    : public UnsafeCondNopTesterA_25Is0_op1_24To20Is0x111 {
+ public:
+  ForbiddenCondNopTester_A_25Is0_op1_24To20Is0x111_Ldrtb_Rule_A1()
+    : UnsafeCondNopTesterA_25Is0_op1_24To20Is0x111(
+      state_.ForbiddenCondNop_Ldrtb_Rule_A1_instance_)
+  {}
+};
+
+class ForbiddenCondNopTester_A_25Is1_op1_24To20Is0x111_B_4Is0_Ldrtb_Rule_A2
+    : public UnsafeCondNopTesterA_25Is1_op1_24To20Is0x111_B_4Is0 {
+ public:
+  ForbiddenCondNopTester_A_25Is1_op1_24To20Is0x111_B_4Is0_Ldrtb_Rule_A2()
+    : UnsafeCondNopTesterA_25Is1_op1_24To20Is0x111_B_4Is0(
+      state_.ForbiddenCondNop_Ldrtb_Rule_A2_instance_)
+  {}
+};
+
 class Store2RegisterImm12OpRnNotRtOnWritebackTester_Flags_24To21Is1001_Rn_19To16Is1101_Imm12_11To0Is000000000100_Push_Rule_123_A2_P248
     : public LoadStore2RegisterImm12OpTesterFlags_24To21Is1001_Rn_19To16Is1101_Imm12_11To0Is000000000100 {
  public:
   Store2RegisterImm12OpRnNotRtOnWritebackTester_Flags_24To21Is1001_Rn_19To16Is1101_Imm12_11To0Is000000000100_Push_Rule_123_A2_P248()
     : LoadStore2RegisterImm12OpTesterFlags_24To21Is1001_Rn_19To16Is1101_Imm12_11To0Is000000000100(
       state_.Store2RegisterImm12OpRnNotRtOnWriteback_Push_Rule_123_A2_P248_instance_)
   {}
 };
 
 class Store2RegisterImm12OpTester_Notcccc010100101101tttt000000000100_Str_Rule_194_A1_P384
@@ skipping 52 matching lines @@
 
 class Binary2RegisterBitRangeNotRnIsPcTester_op1_24To20Is1111x_op2_7To5Isx10_Ubfx_Rule_236_A1_P466
     : public Binary2RegisterBitRangeNotRnIsPcTesterop1_24To20Is1111x_op2_7To5Isx10 {
  public:
   Binary2RegisterBitRangeNotRnIsPcTester_op1_24To20Is1111x_op2_7To5Isx10_Ubfx_Rule_236_A1_P466()
     : Binary2RegisterBitRangeNotRnIsPcTesterop1_24To20Is1111x_op2_7To5Isx10(
       state_.Binary2RegisterBitRangeNotRnIsPc_Ubfx_Rule_236_A1_P466_instance_)
   {}
 };
 
-class Unary1RegisterSetTester_op2_6To4Is000_op_22To21Isx0_Mrs_Rule_102_A1_P206_Or_B6_10
-    : public Unary1RegisterSetTesterop2_6To4Is000_op_22To21Isx0 {
+class ForbiddenCondNopTester_op2_6To4Is000_B_9Is1_op_22To21Isx0_Msr_Rule_Banked_register_A1_B9_1990
+    : public UnsafeCondNopTesterop2_6To4Is000_B_9Is1_op_22To21Isx0 {
  public:
-  Unary1RegisterSetTester_op2_6To4Is000_op_22To21Isx0_Mrs_Rule_102_A1_P206_Or_B6_10()
-    : Unary1RegisterSetTesterop2_6To4Is000_op_22To21Isx0(
+  ForbiddenCondNopTester_op2_6To4Is000_B_9Is1_op_22To21Isx0_Msr_Rule_Banked_register_A1_B9_1990()
+    : UnsafeCondNopTesterop2_6To4Is000_B_9Is1_op_22To21Isx0(
+      state_.ForbiddenCondNop_Msr_Rule_Banked_register_A1_B9_1990_instance_)
+  {}
+};
+
+class ForbiddenCondNopTester_op2_6To4Is000_B_9Is1_op_22To21Isx1_Msr_Rule_Banked_register_A1_B9_1992
+    : public UnsafeCondNopTesterop2_6To4Is000_B_9Is1_op_22To21Isx1 {
+ public:
+  ForbiddenCondNopTester_op2_6To4Is000_B_9Is1_op_22To21Isx1_Msr_Rule_Banked_register_A1_B9_1992()
+    : UnsafeCondNopTesterop2_6To4Is000_B_9Is1_op_22To21Isx1(
+      state_.ForbiddenCondNop_Msr_Rule_Banked_register_A1_B9_1992_instance_)
+  {}
+};
+
+class Unary1RegisterSetTester_op2_6To4Is000_B_9Is0_op_22To21Isx0_Mrs_Rule_102_A1_P206_Or_B6_10
+    : public Unary1RegisterSetTesterop2_6To4Is000_B_9Is0_op_22To21Isx0 {
+ public:
+  Unary1RegisterSetTester_op2_6To4Is000_B_9Is0_op_22To21Isx0_Mrs_Rule_102_A1_P206_Or_B6_10()
+    : Unary1RegisterSetTesterop2_6To4Is000_B_9Is0_op_22To21Isx0(
       state_.Unary1RegisterSet_Mrs_Rule_102_A1_P206_Or_B6_10_instance_)
   {}
 };
 
-class Unary1RegisterUseTester_op2_6To4Is000_op_22To21Is01_op1_19To16Isxx00_Msr_Rule_104_A1_P210
-    : public Unary1RegisterUseTesterop2_6To4Is000_op_22To21Is01_op1_19To16Isxx00 {
+class Unary1RegisterUseTester_op2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx00_Msr_Rule_104_A1_P210
+    : public Unary1RegisterUseTesterop2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx00 {
  public:
-  Unary1RegisterUseTester_op2_6To4Is000_op_22To21Is01_op1_19To16Isxx00_Msr_Rule_104_A1_P210()
-    : Unary1RegisterUseTesterop2_6To4Is000_op_22To21Is01_op1_19To16Isxx00(
+  Unary1RegisterUseTester_op2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx00_Msr_Rule_104_A1_P210()
+    : Unary1RegisterUseTesterop2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx00(
       state_.Unary1RegisterUse_Msr_Rule_104_A1_P210_instance_)
   {}
 };
 
-class ForbiddenCondNopTester_op2_6To4Is000_op_22To21Is01_op1_19To16Isxx01_Msr_Rule_B6_1_7_P14
-    : public UnsafeCondNopTesterop2_6To4Is000_op_22To21Is01_op1_19To16Isxx01 {
+class ForbiddenCondNopTester_op2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx01_Msr_Rule_B6_1_7_P14
+    : public UnsafeCondNopTesterop2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx01 {
  public:
-  ForbiddenCondNopTester_op2_6To4Is000_op_22To21Is01_op1_19To16Isxx01_Msr_Rule_B6_1_7_P14()
-    : UnsafeCondNopTesterop2_6To4Is000_op_22To21Is01_op1_19To16Isxx01(
+  ForbiddenCondNopTester_op2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx01_Msr_Rule_B6_1_7_P14()
+    : UnsafeCondNopTesterop2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx01(
       state_.ForbiddenCondNop_Msr_Rule_B6_1_7_P14_instance_)
   {}
 };
 
-class ForbiddenCondNopTester_op2_6To4Is000_op_22To21Is01_op1_19To16Isxx1x_Msr_Rule_B6_1_7_P14
-    : public UnsafeCondNopTesterop2_6To4Is000_op_22To21Is01_op1_19To16Isxx1x {
+class ForbiddenCondNopTester_op2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx1x_Msr_Rule_B6_1_7_P14
+    : public UnsafeCondNopTesterop2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx1x {
  public:
-  ForbiddenCondNopTester_op2_6To4Is000_op_22To21Is01_op1_19To16Isxx1x_Msr_Rule_B6_1_7_P14()
-    : UnsafeCondNopTesterop2_6To4Is000_op_22To21Is01_op1_19To16Isxx1x(
+  ForbiddenCondNopTester_op2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx1x_Msr_Rule_B6_1_7_P14()
+    : UnsafeCondNopTesterop2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx1x(
       state_.ForbiddenCondNop_Msr_Rule_B6_1_7_P14_instance_)
   {}
 };
 
-class ForbiddenCondNopTester_op2_6To4Is000_op_22To21Is11_Msr_Rule_B6_1_7_P14
-    : public UnsafeCondNopTesterop2_6To4Is000_op_22To21Is11 {
+class ForbiddenCondNopTester_op2_6To4Is000_B_9Is0_op_22To21Is11_Msr_Rule_B6_1_7_P14
+    : public UnsafeCondNopTesterop2_6To4Is000_B_9Is0_op_22To21Is11 {
  public:
-  ForbiddenCondNopTester_op2_6To4Is000_op_22To21Is11_Msr_Rule_B6_1_7_P14()
-    : UnsafeCondNopTesterop2_6To4Is000_op_22To21Is11(
+  ForbiddenCondNopTester_op2_6To4Is000_B_9Is0_op_22To21Is11_Msr_Rule_B6_1_7_P14()
+    : UnsafeCondNopTesterop2_6To4Is000_B_9Is0_op_22To21Is11(
       state_.ForbiddenCondNop_Msr_Rule_B6_1_7_P14_instance_)
   {}
 };
 
 class BranchToRegisterTester_op2_6To4Is001_op_22To21Is01_Bx_Rule_25_A1_P62
     : public BranchToRegisterTesterop2_6To4Is001_op_22To21Is01 {
  public:
   BranchToRegisterTester_op2_6To4Is001_op_22To21Is01_Bx_Rule_25_A1_P62()
     : BranchToRegisterTesterop2_6To4Is001_op_22To21Is01(
       state_.BranchToRegister_Bx_Rule_25_A1_P62_instance_)
@@ skipping 20 matching lines @@
 
 class BranchToRegisterTester_op2_6To4Is011_op_22To21Is01RegsNotPc_Blx_Rule_24_A1_P60
     : public BranchToRegisterTesterop2_6To4Is011_op_22To21Is01RegsNotPc {
  public:
   BranchToRegisterTester_op2_6To4Is011_op_22To21Is01RegsNotPc_Blx_Rule_24_A1_P60()
     : BranchToRegisterTesterop2_6To4Is011_op_22To21Is01RegsNotPc(
       state_.BranchToRegister_Blx_Rule_24_A1_P60_instance_)
   {}
 };
 
+class ForbiddenCondNopTester_op2_6To4Is110_op_22To21Is11_Eret_Rule_A1
+    : public UnsafeCondNopTesterop2_6To4Is110_op_22To21Is11 {
+ public:
+  ForbiddenCondNopTester_op2_6To4Is110_op_22To21Is11_Eret_Rule_A1()
+    : UnsafeCondNopTesterop2_6To4Is110_op_22To21Is11(
+      state_.ForbiddenCondNop_Eret_Rule_A1_instance_)
+  {}
+};
+
 class BreakPointAndConstantPoolHeadTester_op2_6To4Is111_op_22To21Is01_Bkpt_Rule_22_A1_P56
     : public Immediate16UseTesterop2_6To4Is111_op_22To21Is01 {
  public:
   BreakPointAndConstantPoolHeadTester_op2_6To4Is111_op_22To21Is01_Bkpt_Rule_22_A1_P56()
     : Immediate16UseTesterop2_6To4Is111_op_22To21Is01(
       state_.BreakPointAndConstantPoolHead_Bkpt_Rule_22_A1_P56_instance_)
   {}
 };
 
+class ForbiddenCondNopTester_op2_6To4Is111_op_22To21Is10_Hvc_Rule_A1
+    : public UnsafeCondNopTesterop2_6To4Is111_op_22To21Is10 {
+ public:
+  ForbiddenCondNopTester_op2_6To4Is111_op_22To21Is10_Hvc_Rule_A1()
+    : UnsafeCondNopTesterop2_6To4Is111_op_22To21Is10(
+      state_.ForbiddenCondNop_Hvc_Rule_A1_instance_)
+  {}
+};
+
 class ForbiddenCondNopTester_op2_6To4Is111_op_22To21Is11_Smc_Rule_B6_1_9_P18
     : public UnsafeCondNopTesterop2_6To4Is111_op_22To21Is11 {
  public:
   ForbiddenCondNopTester_op2_6To4Is111_op_22To21Is11_Smc_Rule_B6_1_9_P18()
     : UnsafeCondNopTesterop2_6To4Is111_op_22To21Is11(
       state_.ForbiddenCondNop_Smc_Rule_B6_1_9_P18_instance_)
   {}
 };
 
 class CondNopTester_op_22Is0_op1_19To16Is0000_op2_7To0Is00000000_Nop_Rule_110_A1_P222
@@ skipping 43 matching lines @@
 
 class CondNopTester_op_22Is0_op1_19To16Is0000_op2_7To0Is1111xxxx_Dbg_Rule_40_A1_P88
     : public CondNopTesterop_22Is0_op1_19To16Is0000_op2_7To0Is1111xxxx {
  public:
   CondNopTester_op_22Is0_op1_19To16Is0000_op2_7To0Is1111xxxx_Dbg_Rule_40_A1_P88()
     : CondNopTesterop_22Is0_op1_19To16Is0000_op2_7To0Is1111xxxx(
       state_.CondNop_Dbg_Rule_40_A1_P88_instance_)
   {}
 };
 
+class MoveImmediate12ToApsrTester_op_22Is0_op1_19To16Is0100_Msr_Rule_103_A1_P208
+    : public MoveImmediate12ToApsrTesterop_22Is0_op1_19To16Is0100 {
+ public:
+  MoveImmediate12ToApsrTester_op_22Is0_op1_19To16Is0100_Msr_Rule_103_A1_P208()
+    : MoveImmediate12ToApsrTesterop_22Is0_op1_19To16Is0100(
+      state_.MoveImmediate12ToApsr_Msr_Rule_103_A1_P208_instance_)
+  {}
+};
+
+class MoveImmediate12ToApsrTester_op_22Is0_op1_19To16Is1x00_Msr_Rule_103_A1_P208
+    : public MoveImmediate12ToApsrTesterop_22Is0_op1_19To16Is1x00 {
+ public:
+  MoveImmediate12ToApsrTester_op_22Is0_op1_19To16Is1x00_Msr_Rule_103_A1_P208()
+    : MoveImmediate12ToApsrTesterop_22Is0_op1_19To16Is1x00(
+      state_.MoveImmediate12ToApsr_Msr_Rule_103_A1_P208_instance_)
+  {}
+};
+
 class ForbiddenCondNopTester_op_22Is0_op1_19To16Isxx01_Msr_Rule_B6_1_6_A1_PB6_12
     : public UnsafeCondNopTesterop_22Is0_op1_19To16Isxx01 {
  public:
   ForbiddenCondNopTester_op_22Is0_op1_19To16Isxx01_Msr_Rule_B6_1_6_A1_PB6_12()
     : UnsafeCondNopTesterop_22Is0_op1_19To16Isxx01(
       state_.ForbiddenCondNop_Msr_Rule_B6_1_6_A1_PB6_12_instance_)
   {}
 };
 
 class ForbiddenCondNopTester_op_22Is0_op1_19To16Isxx1x_Msr_Rule_B6_1_6_A1_PB6_12
@@ skipping 664 matching lines @@
 
 class Binary4RegisterDualOpTester_op1_22To20Is101_op2_7To5Is11xRegsNotPc_Smmls_Rule_175_P348
     : public Binary4RegisterDualOpTesterop1_22To20Is101_op2_7To5Is11xRegsNotPc {
  public:
   Binary4RegisterDualOpTester_op1_22To20Is101_op2_7To5Is11xRegsNotPc_Smmls_Rule_175_P348()
     : Binary4RegisterDualOpTesterop1_22To20Is101_op2_7To5Is11xRegsNotPc(
       state_.Binary4RegisterDualOp_Smmls_Rule_175_P348_instance_)
   {}
 };
 
+class DeprecatedTester_op_23To20Is0x00_Swp_Swpb_Rule_A1
+    : public UnsafeCondNopTesterop_23To20Is0x00 {
+ public:
+  DeprecatedTester_op_23To20Is0x00_Swp_Swpb_Rule_A1()
+    : UnsafeCondNopTesterop_23To20Is0x00(
+      state_.Deprecated_Swp_Swpb_Rule_A1_instance_)
+  {}
+};
+
 class StoreExclusive3RegisterOpTester_op_23To20Is1000_Strex_Rule_202_A1_P400
     : public StoreExclusive3RegisterOpTesterop_23To20Is1000 {
  public:
   StoreExclusive3RegisterOpTester_op_23To20Is1000_Strex_Rule_202_A1_P400()
     : StoreExclusive3RegisterOpTesterop_23To20Is1000(
       state_.StoreExclusive3RegisterOp_Strex_Rule_202_A1_P400_instance_)
   {}
 };
 
 class LoadExclusive2RegisterOpTester_op_23To20Is1001_Ldrex_Rule_69_A1_P142
@@ skipping 230 matching lines @@
 
 TEST_F(Arm32DecoderStateTests,
        BranchImmediate24Tester_op_25To20Is11xxxx_Bl_Blx_Rule_23_A1_P58_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_Test) {
   BranchImmediate24Tester_op_25To20Is11xxxx_Bl_Blx_Rule_23_A1_P58 baseline_tester;
   NamedBranch_Bl_Blx_Rule_23_A1_P58 actual;
   ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
   a_vs_b_tester.Test("cccc1011iiiiiiiiiiiiiiiiiiiiiiii");
 }
 
 TEST_F(Arm32DecoderStateTests,
+       ForbiddenCondNopTester_op_25Is0_op1_24To20Is0xx1x_op2_7To4Is1011_extra_load_store_instructions_unpriviledged_cccc0000xx1xxxxxxxxxxxxx1011xxxx_Test) {
+  ForbiddenCondNopTester_op_25Is0_op1_24To20Is0xx1x_op2_7To4Is1011_extra_load_store_instructions_unpriviledged baseline_tester;
+  NamedForbidden_extra_load_store_instructions_unpriviledged actual;
+  ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
+  a_vs_b_tester.Test("cccc0000xx1xxxxxxxxxxxxx1011xxxx");
+}
+
+TEST_F(Arm32DecoderStateTests,
+       ForbiddenCondNopTester_op_25Is0_op1_24To20Is0xx1x_op2_7To4Is11x1_extra_load_store_instructions_unpriviledged_cccc0000xx1xxxxxxxxxxxxx11x1xxxx_Test) {
+  ForbiddenCondNopTester_op_25Is0_op1_24To20Is0xx1x_op2_7To4Is11x1_extra_load_store_instructions_unpriviledged baseline_tester;
+  NamedForbidden_extra_load_store_instructions_unpriviledged actual;
+  ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
+  a_vs_b_tester.Test("cccc0000xx1xxxxxxxxxxxxx11x1xxxx");
+}
+
+TEST_F(Arm32DecoderStateTests,
        Unary1RegisterImmediateOpTester_op_25Is1_op1_24To20Is10000RegsNotPc_Mov_Rule_96_A2_P194_cccc00110000iiiiddddIIIIIIIIIIII_Test) {
   Unary1RegisterImmediateOpTester_op_25Is1_op1_24To20Is10000RegsNotPc_Mov_Rule_96_A2_P194 baseline_tester;
   NamedDefs12To15_Mov_Rule_96_A2_P194 actual;
   ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
   a_vs_b_tester.Test("cccc00110000iiiiddddIIIIIIIIIIII");
 }
 
 TEST_F(Arm32DecoderStateTests,
        Unary1RegisterImmediateOpTester_op_25Is1_op1_24To20Is10100RegsNotPc_Mov_Rule_99_A1_P200_cccc00110100iiiiddddIIIIIIIIIIII_Test) {
   Unary1RegisterImmediateOpTester_op_25Is1_op1_24To20Is10100RegsNotPc_Mov_Rule_99_A1_P200 baseline_tester;
@@ skipping 28 matching lines @@
 
 TEST_F(Arm32DecoderStateTests,
        Unary1RegisterImmediateOpTester_op_24To20Is00100_Rn_19To16Is1111_Adr_Rule_10_A2_P32_cccc001001001111ddddiiiiiiiiiiii_Test) {
   Unary1RegisterImmediateOpTester_op_24To20Is00100_Rn_19To16Is1111_Adr_Rule_10_A2_P32 baseline_tester;
   NamedDefs12To15_Adr_Rule_10_A2_P32 actual;
   ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
   a_vs_b_tester.Test("cccc001001001111ddddiiiiiiiiiiii");
 }
 
 TEST_F(Arm32DecoderStateTests,
+       ForbiddenCondNopTester_op_24To20Is00101_Rn_19To16Is1111_Subs_Pc_Lr_and_related_instructions_Rule_A1a_cccc00100101nnnn1111iiiiiiiiiiii_Test) {
+  ForbiddenCondNopTester_op_24To20Is00101_Rn_19To16Is1111_Subs_Pc_Lr_and_related_instructions_Rule_A1a baseline_tester;
+  NamedForbidden_Subs_Pc_Lr_and_related_instructions_Rule_A1a actual;
+  ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
+  a_vs_b_tester.Test("cccc00100101nnnn1111iiiiiiiiiiii");
+}
+
+TEST_F(Arm32DecoderStateTests,
        Binary2RegisterImmediateOpTester_op_24To20Is0011xNotRdIsPcAndS_Rsb_Rule_142_A1_P284_cccc0010011snnnnddddiiiiiiiiiiii_Test) {
   Binary2RegisterImmediateOpTester_op_24To20Is0011xNotRdIsPcAndS_Rsb_Rule_142_A1_P284 baseline_tester;
   NamedDefs12To15_Rsb_Rule_142_A1_P284 actual;
   ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
   a_vs_b_tester.Test("cccc0010011snnnnddddiiiiiiiiiiii");
 }
 
 TEST_F(Arm32DecoderStateTests,
        Binary2RegisterImmediateOpTester_op_24To20Is0100x_NotRn_19To16Is1111NeitherRdIsPcAndSNorRnIsPcAndNotS_Add_Rule_5_A1_P22_cccc0010100snnnnddddiiiiiiiiiiii_Test) {
   Binary2RegisterImmediateOpTester_op_24To20Is0100x_NotRn_19To16Is1111NeitherRdIsPcAndSNorRnIsPcAndNotS_Add_Rule_5_A1_P22 baseline_tester;
   NamedDefs12To15_Add_Rule_5_A1_P22 actual;
   ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
   a_vs_b_tester.Test("cccc0010100snnnnddddiiiiiiiiiiii");
 }
 
 TEST_F(Arm32DecoderStateTests,
        Unary1RegisterImmediateOpTester_op_24To20Is01000_Rn_19To16Is1111_Adr_Rule_10_A1_P32_cccc001010001111ddddiiiiiiiiiiii_Test) {
   Unary1RegisterImmediateOpTester_op_24To20Is01000_Rn_19To16Is1111_Adr_Rule_10_A1_P32 baseline_tester;
   NamedDefs12To15_Adr_Rule_10_A1_P32 actual;
   ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
   a_vs_b_tester.Test("cccc001010001111ddddiiiiiiiiiiii");
 }
 
 TEST_F(Arm32DecoderStateTests,
+       ForbiddenCondNopTester_op_24To20Is01001_Rn_19To16Is1111_Subs_Pc_Lr_and_related_instructions_Rule_A1b_cccc00101001nnnn1111iiiiiiiiiiii_Test) {
+  ForbiddenCondNopTester_op_24To20Is01001_Rn_19To16Is1111_Subs_Pc_Lr_and_related_instructions_Rule_A1b baseline_tester;
+  NamedForbidden_Subs_Pc_Lr_and_related_instructions_Rule_A1b actual;
+  ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
+  a_vs_b_tester.Test("cccc00101001nnnn1111iiiiiiiiiiii");
+}
+
+TEST_F(Arm32DecoderStateTests,
        Binary2RegisterImmediateOpTester_op_24To20Is0101xNotRdIsPcAndS_Adc_Rule_6_A1_P14_cccc0010101snnnnddddiiiiiiiiiiii_Test) {
   Binary2RegisterImmediateOpTester_op_24To20Is0101xNotRdIsPcAndS_Adc_Rule_6_A1_P14 baseline_tester;
   NamedDefs12To15_Adc_Rule_6_A1_P14 actual;
   ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
   a_vs_b_tester.Test("cccc0010101snnnnddddiiiiiiiiiiii");
 }
 
 TEST_F(Arm32DecoderStateTests,
        Binary2RegisterImmediateOpTester_op_24To20Is0110xNotRdIsPcAndS_Sbc_Rule_151_A1_P302_cccc0010110snnnnddddiiiiiiiiiiii_Test) {
   Binary2RegisterImmediateOpTester_op_24To20Is0110xNotRdIsPcAndS_Sbc_Rule_151_A1_P302 baseline_tester;
@@ skipping 680 matching lines @@
 
 TEST_F(Arm32DecoderStateTests,
        Store3RegisterImm5OpTester_A_25Is1_op1_24To20Isxx0x0_B_4Is0_Notop1_repeated_24To20Is0x010_Str_Rule_195_A1_P386_cccc011pd0w0nnnnttttiiiiitt0mmmm_Test) {
   Store3RegisterImm5OpTester_A_25Is1_op1_24To20Isxx0x0_B_4Is0_Notop1_repeated_24To20Is0x010_Str_Rule_195_A1_P386 baseline_tester;
   NamedStoreBasedOffsetMemory_Str_Rule_195_A1_P386 actual;
   ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
   a_vs_b_tester.Test("cccc011pd0w0nnnnttttiiiiitt0mmmm");
 }
 
 TEST_F(Arm32DecoderStateTests,
-       Load2RegisterImm12OpTester_A_25Is0_op1_24To20Isxx0x1_NotRn_19To16Is1111_Notop1_repeated_24To20Is0x011NotRnIsPc_Ldr_Rule_58_A1_P120_cccc010pd0w1nnnnttttiiiiiiiiiiii_Test) {
+       ForbiddenCondNopTester_A_25Is0_op1_24To20Is0x010_Strt_Rule_A1_cccc0100u010nnnnttttiiiiiiiiiiii_Test) {
+  ForbiddenCondNopTester_A_25Is0_op1_24To20Is0x010_Strt_Rule_A1 baseline_tester;
+  NamedForbidden_Strt_Rule_A1 actual;
+  ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
+  a_vs_b_tester.Test("cccc0100u010nnnnttttiiiiiiiiiiii");
+}
+
+TEST_F(Arm32DecoderStateTests,
+       ForbiddenCondNopTester_A_25Is1_op1_24To20Is0x010_B_4Is0_Strt_Rule_A2_cccc0110u010nnnnttttiiiiitt0mmmm_Test) {
+  ForbiddenCondNopTester_A_25Is1_op1_24To20Is0x010_B_4Is0_Strt_Rule_A2 baseline_tester;
+  NamedForbidden_Strt_Rule_A2 actual;
+  ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
+  a_vs_b_tester.Test("cccc0110u010nnnnttttiiiiitt0mmmm");
+}
+
+TEST_F(Arm32DecoderStateTests,
+       Load2RegisterImm12OpTester_A_25Is0_op1_24To20Isxx0x1_NotRn_19To16Is1111_Notop1_repeated_24To20Is0x011NotRnIsPc_Ldr_Rule_58_A1_P120_cccc010pu0w1nnnnttttiiiiiiiiiiii_Test) {
   Load2RegisterImm12OpTester_A_25Is0_op1_24To20Isxx0x1_NotRn_19To16Is1111_Notop1_repeated_24To20Is0x011NotRnIsPc_Ldr_Rule_58_A1_P120 baseline_tester;
   NamedLoadBasedImmedMemory_Ldr_Rule_58_A1_P120 actual;
   ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
-  a_vs_b_tester.Test("cccc010pd0w1nnnnttttiiiiiiiiiiii");
+  a_vs_b_tester.Test("cccc010pu0w1nnnnttttiiiiiiiiiiii");
 }
 
 TEST_F(Arm32DecoderStateTests,
-       Load2RegisterImm12OpTester_A_25Is0_op1_24To20Isxx0x1_Rn_19To16Is1111_Notop1_repeated_24To20Is0x011_Ldr_Rule_59_A1_P122_cccc0101d0011111ttttiiiiiiiiiiii_Test) {
+       Load2RegisterImm12OpTester_A_25Is0_op1_24To20Isxx0x1_Rn_19To16Is1111_Notop1_repeated_24To20Is0x011_Ldr_Rule_59_A1_P122_cccc0101u0011111ttttiiiiiiiiiiii_Test) {
   Load2RegisterImm12OpTester_A_25Is0_op1_24To20Isxx0x1_Rn_19To16Is1111_Notop1_repeated_24To20Is0x011_Ldr_Rule_59_A1_P122 baseline_tester;
   NamedLoadBasedImmedMemory_Ldr_Rule_59_A1_P122 actual;
   ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
-  a_vs_b_tester.Test("cccc0101d0011111ttttiiiiiiiiiiii");
+  a_vs_b_tester.Test("cccc0101u0011111ttttiiiiiiiiiiii");
 }
 
 TEST_F(Arm32DecoderStateTests,
-       Load3RegisterImm5OpTester_A_25Is1_op1_24To20Isxx0x1_B_4Is0_Notop1_repeated_24To20Is0x011_Ldr_Rule_60_A1_P124_cccc011pd0w1nnnnttttiiiiitt0mmmm_Test) {
+       Load3RegisterImm5OpTester_A_25Is1_op1_24To20Isxx0x1_B_4Is0_Notop1_repeated_24To20Is0x011_Ldr_Rule_60_A1_P124_cccc011pu0w1nnnnttttiiiiitt0mmmm_Test) {
   Load3RegisterImm5OpTester_A_25Is1_op1_24To20Isxx0x1_B_4Is0_Notop1_repeated_24To20Is0x011_Ldr_Rule_60_A1_P124 baseline_tester;
   NamedLoadBasedOffsetMemory_Ldr_Rule_60_A1_P124 actual;
   ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
-  a_vs_b_tester.Test("cccc011pd0w1nnnnttttiiiiitt0mmmm");
+  a_vs_b_tester.Test("cccc011pu0w1nnnnttttiiiiitt0mmmm");
 }
 
 TEST_F(Arm32DecoderStateTests,
-       Store2RegisterImm12OpTester_A_25Is0_op1_24To20Isxx1x0_Notop1_repeated_24To20Is0x110_Strb_Rule_197_A1_P390_cccc010pd1w0nnnnttttiiiiiiiiiiii_Test) {
+       ForbiddenCondNopTester_A_25Is0_op1_24To20Is0x011_Ldrt_Rule_A1_cccc0100u011nnnnttttiiiiiiiiiiii_Test) {
+  ForbiddenCondNopTester_A_25Is0_op1_24To20Is0x011_Ldrt_Rule_A1 baseline_tester;
+  NamedForbidden_Ldrt_Rule_A1 actual;
+  ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
+  a_vs_b_tester.Test("cccc0100u011nnnnttttiiiiiiiiiiii");
+}
+
+TEST_F(Arm32DecoderStateTests,
+       ForbiddenCondNopTester_A_25Is1_op1_24To20Is0x011_B_4Is0_Ldrt_Rule_A2_cccc0110u011nnnnttttiiiiitt0mmmm_Test) {
+  ForbiddenCondNopTester_A_25Is1_op1_24To20Is0x011_B_4Is0_Ldrt_Rule_A2 baseline_tester;
+  NamedForbidden_Ldrt_Rule_A2 actual;
+  ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
+  a_vs_b_tester.Test("cccc0110u011nnnnttttiiiiitt0mmmm");
+}
+
+TEST_F(Arm32DecoderStateTests,
+       Store2RegisterImm12OpTester_A_25Is0_op1_24To20Isxx1x0_Notop1_repeated_24To20Is0x110_Strb_Rule_197_A1_P390_cccc010pu1w0nnnnttttiiiiiiiiiiii_Test) {
   Store2RegisterImm12OpTester_A_25Is0_op1_24To20Isxx1x0_Notop1_repeated_24To20Is0x110_Strb_Rule_197_A1_P390 baseline_tester;
   NamedStoreBasedImmedMemory_Strb_Rule_197_A1_P390 actual;
   ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
-  a_vs_b_tester.Test("cccc010pd1w0nnnnttttiiiiiiiiiiii");
+  a_vs_b_tester.Test("cccc010pu1w0nnnnttttiiiiiiiiiiii");
 }
 
 TEST_F(Arm32DecoderStateTests,
-       Store3RegisterImm5OpTester_A_25Is1_op1_24To20Isxx1x0_B_4Is0_Notop1_repeated_24To20Is0x110_Strb_Rule_198_A1_P392_cccc011pd1w0nnnnttttiiiiitt0mmmm_Test) {
+       Store3RegisterImm5OpTester_A_25Is1_op1_24To20Isxx1x0_B_4Is0_Notop1_repeated_24To20Is0x110_Strb_Rule_198_A1_P392_cccc011pu1w0nnnnttttiiiiitt0mmmm_Test) {
   Store3RegisterImm5OpTester_A_25Is1_op1_24To20Isxx1x0_B_4Is0_Notop1_repeated_24To20Is0x110_Strb_Rule_198_A1_P392 baseline_tester;
   NamedStoreBasedOffsetMemory_Strb_Rule_198_A1_P392 actual;
   ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
-  a_vs_b_tester.Test("cccc011pd1w0nnnnttttiiiiitt0mmmm");
+  a_vs_b_tester.Test("cccc011pu1w0nnnnttttiiiiitt0mmmm");
 }
 
 TEST_F(Arm32DecoderStateTests,
-       Load2RegisterImm12OpTester_A_25Is0_op1_24To20Isxx1x1_NotRn_19To16Is1111_Notop1_repeated_24To20Is0x111NotRnIsPc_Ldrb_Rule_62_A1_P128_cccc010pd1w1nnnnttttiiiiiiiiiiii_Test) {
+       ForbiddenCondNopTester_A_25Is0_op1_24To20Is0x110_Strtb_Rule_A1_cccc0100u110nnnnttttiiiiiiiiiiii_Test) {
+  ForbiddenCondNopTester_A_25Is0_op1_24To20Is0x110_Strtb_Rule_A1 baseline_tester;
+  NamedForbidden_Strtb_Rule_A1 actual;
+  ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
+  a_vs_b_tester.Test("cccc0100u110nnnnttttiiiiiiiiiiii");
+}
+
+TEST_F(Arm32DecoderStateTests,
+       ForbiddenCondNopTester_A_25Is1_op1_24To20Is0x110_B_4Is0_Strtb_Rule_A2_cccc0110u110nnnnttttiiiiitt0mmmm_Test) {
+  ForbiddenCondNopTester_A_25Is1_op1_24To20Is0x110_B_4Is0_Strtb_Rule_A2 baseline_tester;
+  NamedForbidden_Strtb_Rule_A2 actual;
+  ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
+  a_vs_b_tester.Test("cccc0110u110nnnnttttiiiiitt0mmmm");
+}
+
+TEST_F(Arm32DecoderStateTests,
+       Load2RegisterImm12OpTester_A_25Is0_op1_24To20Isxx1x1_NotRn_19To16Is1111_Notop1_repeated_24To20Is0x111NotRnIsPc_Ldrb_Rule_62_A1_P128_cccc010pu1w1nnnnttttiiiiiiiiiiii_Test) {
   Load2RegisterImm12OpTester_A_25Is0_op1_24To20Isxx1x1_NotRn_19To16Is1111_Notop1_repeated_24To20Is0x111NotRnIsPc_Ldrb_Rule_62_A1_P128 baseline_tester;
   NamedLoadBasedImmedMemory_Ldrb_Rule_62_A1_P128 actual;
   ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
-  a_vs_b_tester.Test("cccc010pd1w1nnnnttttiiiiiiiiiiii");
+  a_vs_b_tester.Test("cccc010pu1w1nnnnttttiiiiiiiiiiii");
 }
 
 TEST_F(Arm32DecoderStateTests,
-       Load2RegisterImm12OpTester_A_25Is0_op1_24To20Isxx1x1_Rn_19To16Is1111_Notop1_repeated_24To20Is0x111_Ldrb_Rule_63_A1_P130_cccc0101d1011111ttttiiiiiiiiiiii_Test) {
+       Load2RegisterImm12OpTester_A_25Is0_op1_24To20Isxx1x1_Rn_19To16Is1111_Notop1_repeated_24To20Is0x111_Ldrb_Rule_63_A1_P130_cccc0101u1011111ttttiiiiiiiiiiii_Test) {
   Load2RegisterImm12OpTester_A_25Is0_op1_24To20Isxx1x1_Rn_19To16Is1111_Notop1_repeated_24To20Is0x111_Ldrb_Rule_63_A1_P130 baseline_tester;
   NamedLoadBasedImmedMemory_Ldrb_Rule_63_A1_P130 actual;
   ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
-  a_vs_b_tester.Test("cccc0101d1011111ttttiiiiiiiiiiii");
+  a_vs_b_tester.Test("cccc0101u1011111ttttiiiiiiiiiiii");
 }
 
 TEST_F(Arm32DecoderStateTests,
-       Load3RegisterImm5OpTester_A_25Is1_op1_24To20Isxx1x1_B_4Is0_Notop1_repeated_24To20Is0x111_Ldrb_Rule_64_A1_P132_cccc011pd1w1nnnnttttiiiiitt0mmmm_Test) {
+       Load3RegisterImm5OpTester_A_25Is1_op1_24To20Isxx1x1_B_4Is0_Notop1_repeated_24To20Is0x111_Ldrb_Rule_64_A1_P132_cccc011pu1w1nnnnttttiiiiitt0mmmm_Test) {
   Load3RegisterImm5OpTester_A_25Is1_op1_24To20Isxx1x1_B_4Is0_Notop1_repeated_24To20Is0x111_Ldrb_Rule_64_A1_P132 baseline_tester;
   NamedLoadBasedOffsetMemory_Ldrb_Rule_64_A1_P132 actual;
   ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
-  a_vs_b_tester.Test("cccc011pd1w1nnnnttttiiiiitt0mmmm");
+  a_vs_b_tester.Test("cccc011pu1w1nnnnttttiiiiitt0mmmm");
 }
 
 TEST_F(Arm32DecoderStateTests,
+       ForbiddenCondNopTester_A_25Is0_op1_24To20Is0x111_Ldrtb_Rule_A1_cccc0100u111nnnnttttiiiiiiiiiiii_Test) {
+  ForbiddenCondNopTester_A_25Is0_op1_24To20Is0x111_Ldrtb_Rule_A1 baseline_tester;
+  NamedForbidden_Ldrtb_Rule_A1 actual;
+  ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
+  a_vs_b_tester.Test("cccc0100u111nnnnttttiiiiiiiiiiii");
+}
+
+TEST_F(Arm32DecoderStateTests,
+       ForbiddenCondNopTester_A_25Is1_op1_24To20Is0x111_B_4Is0_Ldrtb_Rule_A2_cccc0110u111nnnnttttiiiiitt0mmmm_Test) {
+  ForbiddenCondNopTester_A_25Is1_op1_24To20Is0x111_B_4Is0_Ldrtb_Rule_A2 baseline_tester;
+  NamedForbidden_Ldrtb_Rule_A2 actual;
+  ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
+  a_vs_b_tester.Test("cccc0110u111nnnnttttiiiiitt0mmmm");
+}
+
+TEST_F(Arm32DecoderStateTests,
        Store2RegisterImm12OpRnNotRtOnWritebackTester_Flags_24To21Is1001_Rn_19To16Is1101_Imm12_11To0Is000000000100_Push_Rule_123_A2_P248_cccc010100101101tttt000000000100_Test) {
   Store2RegisterImm12OpRnNotRtOnWritebackTester_Flags_24To21Is1001_Rn_19To16Is1101_Imm12_11To0Is000000000100_Push_Rule_123_A2_P248 tester;
   tester.Test("cccc010100101101tttt000000000100");
 }
 
 TEST_F(Arm32DecoderStateTests,
        Store2RegisterImm12OpTester_Notcccc010100101101tttt000000000100_Str_Rule_194_A1_P384_cccc010pu0w0nnnnttttiiiiiiiiiiii_Test) {
   Store2RegisterImm12OpTester_Notcccc010100101101tttt000000000100_Str_Rule_194_A1_P384 baseline_tester;
   NamedStoreBasedImmedMemory_Str_Rule_194_A1_P384 actual;
   ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
@@ skipping 40 matching lines @@
 
 TEST_F(Arm32DecoderStateTests,
        Binary2RegisterBitRangeNotRnIsPcTester_op1_24To20Is1111x_op2_7To5Isx10_Ubfx_Rule_236_A1_P466_cccc0111111mmmmmddddlllll101nnnn_Test) {
   Binary2RegisterBitRangeNotRnIsPcTester_op1_24To20Is1111x_op2_7To5Isx10_Ubfx_Rule_236_A1_P466 baseline_tester;
   NamedDefs12To15CondsDontCareRdRnNotPc_Ubfx_Rule_236_A1_P466 actual;
   ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
   a_vs_b_tester.Test("cccc0111111mmmmmddddlllll101nnnn");
 }
 
 TEST_F(Arm32DecoderStateTests,
-       Unary1RegisterSetTester_op2_6To4Is000_op_22To21Isx0_Mrs_Rule_102_A1_P206_Or_B6_10_cccc00010r001111dddd000000000000_Test) {
-  Unary1RegisterSetTester_op2_6To4Is000_op_22To21Isx0_Mrs_Rule_102_A1_P206_Or_B6_10 tester;
+       ForbiddenCondNopTester_op2_6To4Is000_B_9Is1_op_22To21Isx0_Msr_Rule_Banked_register_A1_B9_1990_cccc00010r00mmmmdddd001m00000000_Test) {
+  ForbiddenCondNopTester_op2_6To4Is000_B_9Is1_op_22To21Isx0_Msr_Rule_Banked_register_A1_B9_1990 baseline_tester;
+  NamedForbidden_Msr_Rule_Banked_register_A1_B9_1990 actual;
+  ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
+  a_vs_b_tester.Test("cccc00010r00mmmmdddd001m00000000");
+}
+
+TEST_F(Arm32DecoderStateTests,
+       ForbiddenCondNopTester_op2_6To4Is000_B_9Is1_op_22To21Isx1_Msr_Rule_Banked_register_A1_B9_1992_cccc00010r10mmmm1111001m0000nnnn_Test) {
+  ForbiddenCondNopTester_op2_6To4Is000_B_9Is1_op_22To21Isx1_Msr_Rule_Banked_register_A1_B9_1992 baseline_tester;
+  NamedForbidden_Msr_Rule_Banked_register_A1_B9_1992 actual;
+  ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
+  a_vs_b_tester.Test("cccc00010r10mmmm1111001m0000nnnn");
+}
+
+TEST_F(Arm32DecoderStateTests,
+       Unary1RegisterSetTester_op2_6To4Is000_B_9Is0_op_22To21Isx0_Mrs_Rule_102_A1_P206_Or_B6_10_cccc00010r001111dddd000000000000_Test) {
+  Unary1RegisterSetTester_op2_6To4Is000_B_9Is0_op_22To21Isx0_Mrs_Rule_102_A1_P206_Or_B6_10 tester;
   tester.Test("cccc00010r001111dddd000000000000");
 }
 
 TEST_F(Arm32DecoderStateTests,
-       Unary1RegisterUseTester_op2_6To4Is000_op_22To21Is01_op1_19To16Isxx00_Msr_Rule_104_A1_P210_cccc00010010mm00111100000000nnnn_Test) {
-  Unary1RegisterUseTester_op2_6To4Is000_op_22To21Is01_op1_19To16Isxx00_Msr_Rule_104_A1_P210 tester;
+       Unary1RegisterUseTester_op2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx00_Msr_Rule_104_A1_P210_cccc00010010mm00111100000000nnnn_Test) {
+  Unary1RegisterUseTester_op2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx00_Msr_Rule_104_A1_P210 tester;
   tester.Test("cccc00010010mm00111100000000nnnn");
 }
 
 TEST_F(Arm32DecoderStateTests,
-       ForbiddenCondNopTester_op2_6To4Is000_op_22To21Is01_op1_19To16Isxx01_Msr_Rule_B6_1_7_P14_cccc00010010mm01111100000000nnnn_Test) {
-  ForbiddenCondNopTester_op2_6To4Is000_op_22To21Is01_op1_19To16Isxx01_Msr_Rule_B6_1_7_P14 baseline_tester;
+       ForbiddenCondNopTester_op2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx01_Msr_Rule_B6_1_7_P14_cccc00010010mm01111100000000nnnn_Test) {
+  ForbiddenCondNopTester_op2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx01_Msr_Rule_B6_1_7_P14 baseline_tester;
   NamedForbidden_Msr_Rule_B6_1_7_P14 actual;
   ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
   a_vs_b_tester.Test("cccc00010010mm01111100000000nnnn");
 }
 
 TEST_F(Arm32DecoderStateTests,
-       ForbiddenCondNopTester_op2_6To4Is000_op_22To21Is01_op1_19To16Isxx1x_Msr_Rule_B6_1_7_P14_cccc00010010mm1m111100000000nnnn_Test) {
-  ForbiddenCondNopTester_op2_6To4Is000_op_22To21Is01_op1_19To16Isxx1x_Msr_Rule_B6_1_7_P14 baseline_tester;
+       ForbiddenCondNopTester_op2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx1x_Msr_Rule_B6_1_7_P14_cccc00010010mm1m111100000000nnnn_Test) {
+  ForbiddenCondNopTester_op2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx1x_Msr_Rule_B6_1_7_P14 baseline_tester;
   NamedForbidden_Msr_Rule_B6_1_7_P14 actual;
   ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
   a_vs_b_tester.Test("cccc00010010mm1m111100000000nnnn");
 }
 
 TEST_F(Arm32DecoderStateTests,
-       ForbiddenCondNopTester_op2_6To4Is000_op_22To21Is11_Msr_Rule_B6_1_7_P14_cccc00010110mmmm111100000000nnnn_Test) {
-  ForbiddenCondNopTester_op2_6To4Is000_op_22To21Is11_Msr_Rule_B6_1_7_P14 baseline_tester;
+       ForbiddenCondNopTester_op2_6To4Is000_B_9Is0_op_22To21Is11_Msr_Rule_B6_1_7_P14_cccc00010110mmmm111100000000nnnn_Test) {
+  ForbiddenCondNopTester_op2_6To4Is000_B_9Is0_op_22To21Is11_Msr_Rule_B6_1_7_P14 baseline_tester;
   NamedForbidden_Msr_Rule_B6_1_7_P14 actual;
   ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
   a_vs_b_tester.Test("cccc00010110mmmm111100000000nnnn");
 }
 
 TEST_F(Arm32DecoderStateTests,
        BranchToRegisterTester_op2_6To4Is001_op_22To21Is01_Bx_Rule_25_A1_P62_cccc000100101111111111110001mmmm_Test) {
   BranchToRegisterTester_op2_6To4Is001_op_22To21Is01_Bx_Rule_25_A1_P62 baseline_tester;
   NamedBxBlx_Bx_Rule_25_A1_P62 actual;
   ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
@@ skipping 18 matching lines @@
 
 TEST_F(Arm32DecoderStateTests,
        BranchToRegisterTester_op2_6To4Is011_op_22To21Is01RegsNotPc_Blx_Rule_24_A1_P60_cccc000100101111111111110011mmmm_Test) {
   BranchToRegisterTester_op2_6To4Is011_op_22To21Is01RegsNotPc_Blx_Rule_24_A1_P60 baseline_tester;
   NamedBxBlx_Blx_Rule_24_A1_P60 actual;
   ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
   a_vs_b_tester.Test("cccc000100101111111111110011mmmm");
 }
 
 TEST_F(Arm32DecoderStateTests,
+       ForbiddenCondNopTester_op2_6To4Is110_op_22To21Is11_Eret_Rule_A1_cccc0001011000000000000001101110_Test) {
+  ForbiddenCondNopTester_op2_6To4Is110_op_22To21Is11_Eret_Rule_A1 baseline_tester;
+  NamedForbidden_Eret_Rule_A1 actual;
+  ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
+  a_vs_b_tester.Test("cccc0001011000000000000001101110");
+}
+
+TEST_F(Arm32DecoderStateTests,
        BreakPointAndConstantPoolHeadTester_op2_6To4Is111_op_22To21Is01_Bkpt_Rule_22_A1_P56_cccc00010010iiiiiiiiiiii0111iiii_Test) {
   BreakPointAndConstantPoolHeadTester_op2_6To4Is111_op_22To21Is01_Bkpt_Rule_22_A1_P56 baseline_tester;
   NamedBreakpoint_Bkpt_Rule_22_A1_P56 actual;
   ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
   a_vs_b_tester.Test("cccc00010010iiiiiiiiiiii0111iiii");
 }
 
 TEST_F(Arm32DecoderStateTests,
-       ForbiddenCondNopTester_op2_6To4Is111_op_22To21Is11_Smc_Rule_B6_1_9_P18_cccc000101100000000000000111mmmm_Test) {
+       ForbiddenCondNopTester_op2_6To4Is111_op_22To21Is10_Hvc_Rule_A1_cccc00010100iiiiiiiiiiii0111iiii_Test) {
+  ForbiddenCondNopTester_op2_6To4Is111_op_22To21Is10_Hvc_Rule_A1 baseline_tester;
+  NamedForbidden_Hvc_Rule_A1 actual;
+  ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
+  a_vs_b_tester.Test("cccc00010100iiiiiiiiiiii0111iiii");
+}
+
+TEST_F(Arm32DecoderStateTests,
+       ForbiddenCondNopTester_op2_6To4Is111_op_22To21Is11_Smc_Rule_B6_1_9_P18_cccc000101100000000000000111iiii_Test) {
   ForbiddenCondNopTester_op2_6To4Is111_op_22To21Is11_Smc_Rule_B6_1_9_P18 baseline_tester;
   NamedForbidden_Smc_Rule_B6_1_9_P18 actual;
   ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
-  a_vs_b_tester.Test("cccc000101100000000000000111mmmm");
+  a_vs_b_tester.Test("cccc000101100000000000000111iiii");
 }
 
 TEST_F(Arm32DecoderStateTests,
        CondNopTester_op_22Is0_op1_19To16Is0000_op2_7To0Is00000000_Nop_Rule_110_A1_P222_cccc0011001000001111000000000000_Test) {
   CondNopTester_op_22Is0_op1_19To16Is0000_op2_7To0Is00000000_Nop_Rule_110_A1_P222 baseline_tester;
   NamedDontCareInst_Nop_Rule_110_A1_P222 actual;
   ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
   a_vs_b_tester.Test("cccc0011001000001111000000000000");
 }
 
@@ skipping 31 matching lines @@
 
 TEST_F(Arm32DecoderStateTests,
        CondNopTester_op_22Is0_op1_19To16Is0000_op2_7To0Is1111xxxx_Dbg_Rule_40_A1_P88_cccc001100100000111100001111iiii_Test) {
   CondNopTester_op_22Is0_op1_19To16Is0000_op2_7To0Is1111xxxx_Dbg_Rule_40_A1_P88 baseline_tester;
   NamedDontCareInst_Dbg_Rule_40_A1_P88 actual;
   ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
   a_vs_b_tester.Test("cccc001100100000111100001111iiii");
 }
 
 TEST_F(Arm32DecoderStateTests,
+       MoveImmediate12ToApsrTester_op_22Is0_op1_19To16Is0100_Msr_Rule_103_A1_P208_cccc0011001001001111iiiiiiiiiiii_Test) {
+  MoveImmediate12ToApsrTester_op_22Is0_op1_19To16Is0100_Msr_Rule_103_A1_P208 baseline_tester;
+  NamedDontCareInst_Msr_Rule_103_A1_P208 actual;
+  ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
+  a_vs_b_tester.Test("cccc0011001001001111iiiiiiiiiiii");
+}
+
+TEST_F(Arm32DecoderStateTests,
+       MoveImmediate12ToApsrTester_op_22Is0_op1_19To16Is1x00_Msr_Rule_103_A1_P208_cccc001100101x001111iiiiiiiiiiii_Test) {
+  MoveImmediate12ToApsrTester_op_22Is0_op1_19To16Is1x00_Msr_Rule_103_A1_P208 baseline_tester;
+  NamedDontCareInst_Msr_Rule_103_A1_P208 actual;
+  ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
+  a_vs_b_tester.Test("cccc001100101x001111iiiiiiiiiiii");
+}
+
+TEST_F(Arm32DecoderStateTests,
        ForbiddenCondNopTester_op_22Is0_op1_19To16Isxx01_Msr_Rule_B6_1_6_A1_PB6_12_cccc00110010ii011111iiiiiiiiiiii_Test) {
   ForbiddenCondNopTester_op_22Is0_op1_19To16Isxx01_Msr_Rule_B6_1_6_A1_PB6_12 baseline_tester;
   NamedForbidden_Msr_Rule_B6_1_6_A1_PB6_12 actual;
   ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
   a_vs_b_tester.Test("cccc00110010ii011111iiiiiiiiiiii");
 }
 
 TEST_F(Arm32DecoderStateTests,
        ForbiddenCondNopTester_op_22Is0_op1_19To16Isxx1x_Msr_Rule_B6_1_6_A1_PB6_12_cccc00110010ii1i1111iiiiiiiiiiii_Test) {
   ForbiddenCondNopTester_op_22Is0_op1_19To16Isxx1x_Msr_Rule_B6_1_6_A1_PB6_12 baseline_tester;
@@ skipping 588 matching lines @@
 
 TEST_F(Arm32DecoderStateTests,
        Binary4RegisterDualOpTester_op1_22To20Is101_op2_7To5Is11xRegsNotPc_Smmls_Rule_175_P348_cccc01110101ddddaaaammmm11x1nnnn_Test) {
   Binary4RegisterDualOpTester_op1_22To20Is101_op2_7To5Is11xRegsNotPc_Smmls_Rule_175_P348 baseline_tester;
   NamedDefs16To19CondsDontCareRdRaRmRnNotPc_Smmls_Rule_175_P348 actual;
   ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
   a_vs_b_tester.Test("cccc01110101ddddaaaammmm11x1nnnn");
 }
 
 TEST_F(Arm32DecoderStateTests,
+       DeprecatedTester_op_23To20Is0x00_Swp_Swpb_Rule_A1_cccc00010b00nnnntttt00001001tttt_Test) {
+  DeprecatedTester_op_23To20Is0x00_Swp_Swpb_Rule_A1 tester;
+  tester.Test("cccc00010b00nnnntttt00001001tttt");
+}
+
+TEST_F(Arm32DecoderStateTests,
        StoreExclusive3RegisterOpTester_op_23To20Is1000_Strex_Rule_202_A1_P400_cccc00011000nnnndddd11111001tttt_Test) {
   StoreExclusive3RegisterOpTester_op_23To20Is1000_Strex_Rule_202_A1_P400 baseline_tester;
   NamedStoreBasedMemoryRtBits0To3_Strex_Rule_202_A1_P400 actual;
   ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
   a_vs_b_tester.Test("cccc00011000nnnndddd11111001tttt");
 }
 
 TEST_F(Arm32DecoderStateTests,
        LoadExclusive2RegisterOpTester_op_23To20Is1001_Ldrex_Rule_69_A1_P142_cccc00011001nnnntttt111110011111_Test) {
   LoadExclusive2RegisterOpTester_op_23To20Is1001_Ldrex_Rule_69_A1_P142 baseline_tester;
@@ skipping 20 matching lines @@
 
 TEST_F(Arm32DecoderStateTests,
        StoreExclusive3RegisterOpTester_op_23To20Is1100_Strexb_Rule_203_A1_P402_cccc00011100nnnndddd11111001tttt_Test) {
   StoreExclusive3RegisterOpTester_op_23To20Is1100_Strexb_Rule_203_A1_P402 baseline_tester;
   NamedStoreBasedMemoryRtBits0To3_Strexb_Rule_203_A1_P402 actual;
   ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
   a_vs_b_tester.Test("cccc00011100nnnndddd11111001tttt");
 }
 
 TEST_F(Arm32DecoderStateTests,
-       LoadExclusive2RegisterOpTester_op_23To20Is1101_Ldrexb_Rule_70_A1_P144_cccc00011101nnnndddd111110011111_Test) {
+       LoadExclusive2RegisterOpTester_op_23To20Is1101_Ldrexb_Rule_70_A1_P144_cccc00011101nnnntttt111110011111_Test) {
   LoadExclusive2RegisterOpTester_op_23To20Is1101_Ldrexb_Rule_70_A1_P144 baseline_tester;
   NamedLoadBasedMemory_Ldrexb_Rule_70_A1_P144 actual;
   ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
-  a_vs_b_tester.Test("cccc00011101nnnndddd111110011111");
+  a_vs_b_tester.Test("cccc00011101nnnntttt111110011111");
 }
 
 TEST_F(Arm32DecoderStateTests,
        StoreExclusive3RegisterOpTester_op_23To20Is1110_Strexh_Rule_205_A1_P406_cccc00011110nnnndddd11111001tttt_Test) {
   StoreExclusive3RegisterOpTester_op_23To20Is1110_Strexh_Rule_205_A1_P406 baseline_tester;
   NamedStoreBasedMemoryRtBits0To3_Strexh_Rule_205_A1_P406 actual;
   ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
   a_vs_b_tester.Test("cccc00011110nnnndddd11111001tttt");
 }
 
@@ skipping 56 matching lines @@
   ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
   a_vs_b_tester.Test("1111101hiiiiiiiiiiiiiiiiiiiiiiii");
 }
 
 }  // namespace nacl_arm_test
 
 int main(int argc, char* argv[]) {
   testing::InitGoogleTest(&argc, argv);
   return RUN_ALL_TESTS();
 }