ARM validator: continue with extra_load_store_instructions.

src/trusted/validator_arm/baseline_classes.cc

 /*
  * Copyright (c) 2012 The Native Client Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "native_client/src/trusted/validator_arm/baseline_classes.h"
 
 #include <assert.h>
 #include <string.h>
@@ skipping 64 matching lines @@
 bool BranchImmediate24::is_relative_branch(Instruction i) const {
   UNREFERENCED_PARAMETER(i);
   return true;
 }
 
 int32_t BranchImmediate24::branch_target_offset(Instruction i) const {
   return imm24.relative_address(i);
 }
 
 // BreakPointAndConstantPoolHead
+SafetyLevel BreakPointAndConstantPoolHead::safety(const Instruction i) const {
+  return i.GetCondition() == Instruction::AL
+      ? MAY_BE_SAFE
+      : UNPREDICTABLE;
+}
+
 bool BreakPointAndConstantPoolHead::
 is_literal_pool_head(const Instruction i) const {
   return i.GetCondition() == Instruction::AL &&
       value(i) == 0x7777;
 }
 
 // BranchToRegister
 SafetyLevel BranchToRegister::safety(const Instruction i) const {
+  // Extra NaCl constraint: can't branch to PC. This would branch to 8 bytes
+  // after the current instruction. This instruction should be in an instruction
+  // pair, the mask should therefore be to PC and fail checking, but there's
+  // little harm in checking.
+  if (m.reg(i).Equals(kRegisterPc)) return FORBIDDEN_OPERANDS;
+
+  // Redundant with the above, but this is actually UNPREDICTABLE. Expect DCE.
   if (link_register.IsUpdated(i) && m.reg(i).Equals(kRegisterPc)) {
     return UNPREDICTABLE;
   }
 
   return MAY_BE_SAFE;
 }
 
 RegisterList BranchToRegister::defs(const Instruction i) const {
   return RegisterList(kRegisterPc).
       Add(link_register.IsUpdated(i) ? kRegisterLink : kRegisterNone);
@@ skipping 247 matching lines @@
     return UNPREDICTABLE;
   }
 
   if (HasWriteBack(i) &&
       (n.reg(i).Equals(kRegisterPc) ||
        // NOTE: The manual states that that it is also unpredictable
        // when HasWriteBack(i) and Rn=Rt. However, the compilers
        // may not check for this. For the moment, we are changing
        // the code to ignore this case for stores.
        // TODO(karl): Should we not allow this?
+       // TODO(jfb) Fix this.
        (is_load_ && n.reg(i).Equals(t.reg(i))))) {
     return UNPREDICTABLE;
   }
 
   // Above implies literal loads can't writeback, the following checks the
   // ARM restriction that literal loads can't have P == W.
   // This should always decode to another instruction, but checking it is good.
   if (n.reg(i).Equals(kRegisterPc) &&
       (indexing.IsDefined(i) == writes.IsDefined(i))) {
     return UNPREDICTABLE;
@@ skipping 73 matching lines @@
 // LoadStore2RegisterImm12Op
 SafetyLevel LoadStore2RegisterImm12Op::safety(const Instruction i) const {
   // Arm restrictions for this instruction.
   if (HasWriteBack(i) &&
       (n.reg(i).Equals(kRegisterPc) ||
        // NOTE: The manual states that that it is also unpredictable
        // when HasWriteBack(i) and Rn=Rt. However, the compilers
        // may not check for this. For the moment, we are changing
        // the code to ignore this case for stores.
        // TODO(karl): Should we not allow this?
+       // TODO(jfb) Fix this. Once this is fixed,
+       //           Store2RegisterImm12OpRnNotRtOnWriteback becomes redundant
+       //           with this class and can be removed.
        (is_load_ && n.reg(i).Equals(t.reg(i))))) {
     return UNPREDICTABLE;
   }
 
   // Don't allow modification of PC (NaCl constraint).
   if (defs(i).Contains(kRegisterPc)) return FORBIDDEN_OPERANDS;
 
   // NaCl special restriction to make all load/store immediates behave
   // the same.
   if (t.reg(i).Equals(kRegisterPc)) {
@@ skipping 24 matching lines @@
 }
 
 // Store2RegisterImm12Op
 RegisterList Store2RegisterImm12Op::defs(Instruction i) const {
   return immediate_addressing_defs(i);
 }
 
 // Store2RegisterImm12OpRnNotRtOnWriteback
 SafetyLevel Store2RegisterImm12OpRnNotRtOnWriteback::
 safety(Instruction i) const {
+  // TODO(jfb) Redundant with LoadStore2RegisterImm12Op, once it is fixed.
   if (HasWriteBack(i) && (n.reg(i).Equals(t.reg(i))))
     return UNPREDICTABLE;
   return Store2RegisterImm12Op::safety(i);
 }
 
 // LoadStoreRegisterList
 SafetyLevel LoadStoreRegisterList::safety(const Instruction i) const {
   if (n.reg(i).Equals(kRegisterPc) || (register_list.value(i) == 0)) {
     return UNPREDICTABLE;
   }
@@ skipping 151 matching lines @@
     return UNPREDICTABLE;
   }
 
   if (HasWriteBack(i) &&
       (n.reg(i).Equals(kRegisterPc) ||
        // NOTE: The manual states that that it is also unpredictable
        // when HasWriteBack(i) and Rn=Rt. However, the compilers
        // may not check for this. For the moment, we are changing
        // the code to ignore this case for stores.
        // TODO(karl): Should we not allow this?
+       // TODO(jfb) Fix this.
        (is_load_ && n.reg(i).Equals(t.reg(i))))) {
     return UNPREDICTABLE;
   }
 
+  // TODO(jfb) if ArchVersion() < 6 && wback && m == n then UNPREDICTABLE;
+
   // Don't let addressing writeback alter PC (NaCl constraint).
   if (defs(i).Contains(kRegisterPc)) return FORBIDDEN_OPERANDS;
 
   return MAY_BE_SAFE;
 }
 
 Register LoadStore3RegisterOp::base_address_register(
     const Instruction i) const {
   return n.reg(i);
 }
@@ skipping 25 matching lines @@
 
   if (RegisterList(t2.reg(i)).Add(m.reg(i)).Contains(kRegisterPc)) {
     return UNPREDICTABLE;
   }
 
   // NOTE: The manual states that that it is also unpredictable
   // when HasWriteBack(i) and Rn=Rt2. However, the compilers
   // may not check for this. For the moment, we are changing
   // the code to ignore this case for stores.
   // TODO(karl): Should we not allow this?
+  // TODO(jfb) Fix this.
   if (is_load_ && HasWriteBack(i) && n.reg(i).Equals(t2.reg(i))) {
     return UNPREDICTABLE;
   }
 
+  if (is_load_ && (m.reg(i).Equals(t.reg(i)) || m.reg(i).Equals(t2.reg(i)))) {
+    return UNPREDICTABLE;
+  }
+
   // Now apply non-double width restrictions for this instruction.
   return LoadStore3RegisterOp::safety(i);
 }
 
 // StoreExclusive3RegisterOp
 SafetyLevel StoreExclusive3RegisterOp::safety(const Instruction i) const {
   // Arm restrictions for this instruction.
   if (RegisterList(d.reg(i)).Add(t.reg(i)).Add(n.reg(i)).
       Contains(kRegisterPc)) {
     return UNPREDICTABLE;
@@ skipping 70 matching lines @@
     return UNPREDICTABLE;
   }
 
   if (HasWriteBack(i) &&
       (n.reg(i).Equals(kRegisterPc) ||
        // NOTE: The manual states that that it is also unpredictable
        // when HasWriteBack(i) and Rn=Rt2. However, the compilers
        // may not check for this. For the moment, we are changing
        // the code to ignore this case for stores.
        // TODO(karl): Should we not allow this?
+       // TODO(jfb) Fix this.
        (is_load_ && n.reg(i).Equals(t.reg(i))))) {
     return UNPREDICTABLE;
   }
 
   // Don't let Rt be Pc (NaCl constraint -- See header file for special
   // note).
   if (t.reg(i).Equals(kRegisterPc)) {
     return FORBIDDEN_OPERANDS;
   }
 
   // Don't let addressing writeback alter PC (NaCl constraint).
   if (defs(i).Contains(kRegisterPc)) return FORBIDDEN_OPERANDS;
 
+  // TODO(jfb) if ArchVersion() < 6 && wback && m == n then UNPREDICTABLE;
+
   return MAY_BE_SAFE;
 }
 
 Register LoadStore3RegisterImm5Op::base_address_register(
     const Instruction i) const {
   return n.reg(i);
 }
 
 // Load3RegisterImm5Op
 RegisterList Load3RegisterImm5Op::defs(const Instruction i) const {
@@ skipping 215 matching lines @@
   if (be_value(i) == 0x3)
     return UNDEFINED;
 
   if (t.reg(i).Equals(kRegisterPc))
     return UNPREDICTABLE;
 
   return CondVfpOp::safety(i);
 }
 
 }  // namespace nacl_arm_dec