ARM validator: continue with extra_load_store_instructions.

src/trusted/validator_arm/actual_classes.cc

 /*
  * Copyright (c) 2012 The Native Client Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "native_client/src/trusted/validator_arm/actual_classes.h"
 
 #include <assert.h>
 #include <string.h>
@@ skipping 323 matching lines @@
   }
 
   if (t2.reg(i).Equals(kRegisterPc)) {
     return UNPREDICTABLE;
   }
 
   if (HasWriteBack(i) && n.reg(i).Equals(t2.reg(i))) {
     return UNPREDICTABLE;
   }
 
+  if (m.reg(i).Equals(t.reg(i)) || m.reg(i).Equals(t2.reg(i))) {
+    return UNPREDICTABLE;
+  }
+
   // Now apply non-double width restrictions for this instruction.
   return LoadBasedOffsetMemory::safety(i);
 }
 
 RegisterList LoadBasedOffsetMemoryDouble::defs(Instruction i) const {
   return LoadBasedOffsetMemory::defs(i).Add(t2.reg(i));
 }
 
 RegisterList LoadBasedImmedMemory::
 immediate_addressing_defs(const Instruction i) const {
@@ skipping 33 matching lines @@
     return UNPREDICTABLE;
   }
 
   if (HasWriteBack(i) &&
       (n.reg(i).Equals(kRegisterPc))) {
     // NOTE: The manual states that that it is also unpredictable
     // when HasWriteBack(i) and Rn=Rt. However, the compilers
     // may not check for this. For the moment, we are changing
     // the code to ignore this case for stores.
     // TODO(karl): Should we not allow this?
+    // TODO(jfb) Fix this.
     return UNPREDICTABLE;
   }
 
   // Don't let addressing writeback alter PC (NaCl constraint).
   if (defs(i).Contains(kRegisterPc)) return FORBIDDEN_OPERANDS;
 
   return MAY_BE_SAFE;
 }
 
 RegisterList StoreBasedMemoryWithWriteBack::defs(const Instruction i) const {
@@ skipping 14 matching lines @@
     return UNPREDICTABLE;
   }
 
   if (HasWriteBack(i) &&
       (n.reg(i).Equals(kRegisterPc))) {
     // NOTE: The manual states that that it is also unpredictable
     // when HasWriteBack(i) and Rn=Rt. However, the compilers
     // may not check for this. For the moment, we are changing
     // the code to ignore this case for stores.
     // TODO(karl): Should we not allow this?
+    // TODO(jfb) Fix this.
     return UNPREDICTABLE;
   }
 
+  // TODO(jfb) if ArchVersion() < 6 && wback && m == n then UNPREDICTABLE;
+
   return StoreBasedMemoryWithWriteBack::safety(i);
 }
 
 SafetyLevel StoreBasedOffsetMemoryDouble::safety(const Instruction i) const {
   // Arm double width restrictions for this instruction.
   if (!t.IsEven(i)) {
     return UNDEFINED;
   }
 
   if (RegisterList(t2.reg(i)).Add(m.reg(i)).Contains(kRegisterPc)) {
@@ skipping 62 matching lines @@
   UNREFERENCED_PARAMETER(i);
   return MAY_BE_SAFE;
 }
 
 RegisterList Roadblock::defs(Instruction i) const {
   UNREFERENCED_PARAMETER(i);
   return RegisterList();
 }
 
 // Breakpoint
+SafetyLevel Breakpoint::safety(Instruction i) const {
+  return i.GetCondition() == Instruction::AL
+      ? MAY_BE_SAFE
+      : UNPREDICTABLE;
+}
+
 bool Breakpoint::is_literal_pool_head(const Instruction i) const {
   return i.GetCondition() == Instruction::AL
       && i.Bits(19, 8) == 0x777
       && i.Bits(3, 0) == 0x7;
 }
 
 SafetyLevel PackSatRev::safety(const Instruction i) const {
   if (defs(i).Contains(kRegisterPc)) {
     return FORBIDDEN_OPERANDS;
   }
@@ skipping 174 matching lines @@
 }
 
 
 RegisterList MoveDoubleFromCoprocessor::defs(Instruction i) const {
   return RegisterList(Rt(i)).Add(Rt2(i));
 }
 
 // Control flow
 
 SafetyLevel BxBlx::safety(Instruction i) const {
+  // Extra NaCl constraint: can't branch to PC. This would branch to 8 bytes
+  // after the current instruction. This instruction should be in an instruction
+  // pair, the mask should therefore be to PC and fail checking, but there's
+  // little harm in checking.
+  if (m.reg(i).Equals(kRegisterPc)) return FORBIDDEN_OPERANDS;
+
+  // Redundant with the above, but this is actually UNPREDICTABLE. Expect DCE.
   if (link_register.IsUpdated(i) && m.reg(i).Equals(kRegisterPc)) {
     return UNPREDICTABLE;
   }
 
   return MAY_BE_SAFE;
 }
 
 RegisterList BxBlx::defs(const Instruction i) const {
   return RegisterList(kRegisterPc).
       Add(link_register.IsUpdated(i) ? kRegisterLink : kRegisterNone);
@@ skipping 79 matching lines @@
   int width = msbit + 1 - lsbit;
   if (width == 32) {
     return mask == 0;
   } else {
     uint32_t bit_mask = (((1 << width) - 1) << lsbit);
     return (bit_mask & mask) == mask;
   }
 }
 
 }  // namespace nacl_arm_dec