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| 1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
| 2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
| 3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
| 4 // met: | 4 // met: |
| 5 // | 5 // |
| 6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
| 7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
| 8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
| 9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
| 10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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| 5391 | 5391 |
| 5392 // Double value is >= 255, return 255. | 5392 // Double value is >= 255, return 255. |
| 5393 bind(&above_zero); | 5393 bind(&above_zero); |
| 5394 Move(temp_double_reg, 255.0); | 5394 Move(temp_double_reg, 255.0); |
| 5395 BranchF(&in_bounds, NULL, le, input_reg, temp_double_reg); | 5395 BranchF(&in_bounds, NULL, le, input_reg, temp_double_reg); |
| 5396 li(result_reg, Operand(255)); | 5396 li(result_reg, Operand(255)); |
| 5397 Branch(&done); | 5397 Branch(&done); |
| 5398 | 5398 |
| 5399 // In 0-255 range, round and truncate. | 5399 // In 0-255 range, round and truncate. |
| 5400 bind(&in_bounds); | 5400 bind(&in_bounds); |
| 5401 round_w_d(temp_double_reg, input_reg); | 5401 cvt_w_d(temp_double_reg, input_reg); |
| 5402 mfc1(result_reg, temp_double_reg); | 5402 mfc1(result_reg, temp_double_reg); |
| 5403 bind(&done); | 5403 bind(&done); |
| 5404 } | 5404 } |
| 5405 | 5405 |
| 5406 | 5406 |
| 5407 bool AreAliased(Register r1, Register r2, Register r3, Register r4) { | 5407 bool AreAliased(Register r1, Register r2, Register r3, Register r4) { |
| 5408 if (r1.is(r2)) return true; | 5408 if (r1.is(r2)) return true; |
| 5409 if (r1.is(r3)) return true; | 5409 if (r1.is(r3)) return true; |
| 5410 if (r1.is(r4)) return true; | 5410 if (r1.is(r4)) return true; |
| 5411 if (r2.is(r3)) return true; | 5411 if (r2.is(r3)) return true; |
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| 5465 opcode == BGTZL); | 5465 opcode == BGTZL); |
| 5466 opcode = (cond == eq) ? BEQ : BNE; | 5466 opcode = (cond == eq) ? BEQ : BNE; |
| 5467 instr = (instr & ~kOpcodeMask) | opcode; | 5467 instr = (instr & ~kOpcodeMask) | opcode; |
| 5468 masm_.emit(instr); | 5468 masm_.emit(instr); |
| 5469 } | 5469 } |
| 5470 | 5470 |
| 5471 | 5471 |
| 5472 } } // namespace v8::internal | 5472 } } // namespace v8::internal |
| 5473 | 5473 |
| 5474 #endif // V8_TARGET_ARCH_MIPS | 5474 #endif // V8_TARGET_ARCH_MIPS |
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