Refactor Math.min/max to be a single HInstruction.

src/arm/assembler-arm.cc

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
 // are met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 2384 matching lines @@
                       const DwVfpRegister src,
                       const Condition cond) {
   // cond(31-28) | 11101 (27-23)| D=?(22) | 11 (21-20) | 0001 (19-16) |
   // Vd(15-12) | 101(11-9) | sz(8)=1 | 11 (7-6) | M(5)=? | 0(4) | Vm(3-0)
   ASSERT(CpuFeatures::IsEnabled(VFP2));
   emit(cond | 0xE*B24 | B23 | 0x3*B20 | B16 |
        dst.code()*B12 | 0x5*B9 | B8 | 3*B6 | src.code());
 }
 
 
+void Assembler::vorr(const DwVfpRegister dst,
+                     const DwVfpRegister src1,
+                     const DwVfpRegister src2) {
+  // Instruction details available in ARM DDI 0406A, A8-680.
+  // 1111 (31-28) | 00100 (27-23) | D=?(22) | 10 (21-20) | Vn(19-16) |
+  // Vd(15-12) | 0001 (11-8) | N=?(7) | Q=?(6) | M=?(5) | 1 (4) | Vm (3-0)
+  ASSERT(CpuFeatures::IsEnabled(VFP2));
+  emit((0xF << 28) | B25 | B21 | src1.code()*B16 |
+       dst.code()*B12 | B8 | B4 | src2.code());
+}
+
+
 // Pseudo instructions.
 void Assembler::nop(int type) {
   // This is mov rx, rx.
   ASSERT(0 <= type && type <= 14);  // mov pc, pc is not a nop.
   emit(al | 13*B21 | type*B12 | type);
 }
 
 
 bool Assembler::IsNop(Instr instr, int type) {
   // Check for mov rx, rx where x = type.
@@ skipping 266 matching lines @@
 
   // Since a constant pool was just emitted, move the check offset forward by
   // the standard interval.
   next_buffer_check_ = pc_offset() + kCheckPoolInterval;
 }
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_ARM