Change TRACE_ALLOC to take a statement rather than an argument list.

runtime/vm/flow_graph_allocator.cc

 // Copyright (c) 2012, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/flow_graph_allocator.h"
 
 #include "vm/bit_vector.h"
 #include "vm/intermediate_language.h"
 #include "vm/il_printer.h"
 #include "vm/flow_graph_builder.h"
 #include "vm/flow_graph_compiler.h"
 #include "vm/parser.h"
 
 namespace dart {
 
 DEFINE_FLAG(bool, print_ssa_liveness, false,
             "Print liveness for ssa variables.");
 DEFINE_FLAG(bool, trace_ssa_allocator, false,
             "Trace register allocation over SSA.");
 DEFINE_FLAG(bool, print_ssa_liveranges, false,
             "Print live ranges after allocation.");
 
 #if defined(DEBUG)
-#define TRACE_ALLOC(m) do {                     \
-    if (FLAG_trace_ssa_allocator) OS::Print m ; \
+#define TRACE_ALLOC(statement)                                                 \
+  do {                                                                         \
+    if (FLAG_trace_ssa_allocator) statement;                                   \
   } while (0)
 #else
-#define TRACE_ALLOC(m)
+#define TRACE_ALLOC(statement)
 #endif
 
 
 static const intptr_t kNoVirtualRegister = -1;
 static const intptr_t kTempVirtualRegister = -2;
 static const intptr_t kIllegalPosition = -1;
 static const intptr_t kMaxPosition = 0x7FFFFFFF;
 
 
 static intptr_t MinPosition(intptr_t a, intptr_t b) {
@@ skipping 1129 matching lines @@
   }
 
   UseInterval* last_use_interval = (last_before_split == last_use_interval_) ?
     first_after_split : last_use_interval_;
   next_sibling_ = new LiveRange(vreg(),
                                 first_use_after_split,
                                 first_after_split,
                                 last_use_interval,
                                 next_sibling_);
 
-  TRACE_ALLOC(("  split sibling [%d, %d)\n",
-               next_sibling_->Start(), next_sibling_->End()));
+  TRACE_ALLOC(OS::Print("  split sibling [%d, %d)\n",
+                        next_sibling_->Start(), next_sibling_->End()));
 
   last_use_interval_ = last_before_split;
   last_use_interval_->next_ = NULL;
   return next_sibling_;
 }
 
 
 LiveRange* FlowGraphAllocator::SplitBetween(LiveRange* range,
                                             intptr_t from,
                                             intptr_t to) {
-  TRACE_ALLOC(("split %d [%d, %d) between [%d, %d)\n",
-               range->vreg(), range->Start(), range->End(), from, to));
+  TRACE_ALLOC(OS::Print("split %d [%d, %d) between [%d, %d)\n",
+                        range->vreg(), range->Start(), range->End(), from, to));
 
   intptr_t split_pos = kIllegalPosition;
 
   BlockInfo* split_block = BlockInfoAt(to);
   if (from < split_block->entry()->lifetime_position()) {
     // Interval [from, to) spans multiple blocks.
 
     // If last block is inside a loop prefer splitting at outermost loop's
     // header.
     BlockInfo* loop_header = split_block->loop();
@@ skipping 16 matching lines @@
   ASSERT((split_pos != kIllegalPosition) && (from < split_pos));
 
   return range->SplitAt(split_pos);
 }
 
 
 void FlowGraphAllocator::SpillBetween(LiveRange* range,
                                       intptr_t from,
                                       intptr_t to) {
   ASSERT(from < to);
-  TRACE_ALLOC(("spill %d [%d, %d) between [%d, %d)\n",
-               range->vreg(), range->Start(), range->End(), from, to));
+  TRACE_ALLOC(OS::Print("spill %d [%d, %d) between [%d, %d)\n",
+                        range->vreg(), range->Start(), range->End(), from, to));
   LiveRange* tail = range->SplitAt(from);
 
   if (tail->Start() < to) {
     // There is an intersection of tail and [from, to).
     LiveRange* tail_tail = SplitBetween(tail, tail->Start(), to);
     Spill(tail);
     AddToUnallocated(tail_tail);
   } else {
     // No intersection between tail and [from, to).
     AddToUnallocated(tail);
   }
 }
 
 
 void FlowGraphAllocator::SpillAfter(LiveRange* range, intptr_t from) {
-  TRACE_ALLOC(("spill %d [%d, %d) after %d\n",
-               range->vreg(), range->Start(), range->End(), from));
+  TRACE_ALLOC(OS::Print("spill %d [%d, %d) after %d\n",
+                        range->vreg(), range->Start(), range->End(), from));
   LiveRange* tail = range->SplitAt(from);
   Spill(tail);
 }
 
 
 void FlowGraphAllocator::AllocateSpillSlotFor(LiveRange* range) {
   ASSERT(range->spill_slot().IsInvalid());
 
   intptr_t idx = 0;
   for (; idx < spill_slots_.length(); idx++) {
@@ skipping 54 matching lines @@
   // TODO(vegorov): ensure that phis are hinted on the back edge.
   Location hint = unallocated->finger()->FirstHint();
   if (!hint.IsInvalid()) {
     ASSERT(hint.IsRegister());
 
     if (!blocked_cpu_regs_[hint.reg()]) {
       free_until = FirstIntersectionWithAllocated(hint.reg(), unallocated);
       candidate = hint.reg();
     }
 
-    TRACE_ALLOC(("found hint %s for %d: free until %d\n",
-                 hint.Name(), unallocated->vreg(), free_until));
+    TRACE_ALLOC(OS::Print("found hint "));
+    TRACE_ALLOC(hint.Print());
+    TRACE_ALLOC(OS::Print(" for %d: free until %d\n",
+                          unallocated->vreg(), free_until));
   }
 
   if (free_until != kMaxPosition) {
     for (intptr_t reg = 0; reg < kNumberOfCpuRegisters; ++reg) {
       if (!blocked_cpu_regs_[reg] && cpu_regs_[reg].length() == 0) {
         candidate = static_cast<Register>(reg);
         free_until = kMaxPosition;
         break;
       }
     }
@@ skipping 11 matching lines @@
         candidate = static_cast<Register>(reg);
         free_until = intersection;
         if (free_until == kMaxPosition) break;
       }
     }
   }
 
   // All registers are blocked by active ranges.
   if (free_until <= unallocated->Start()) return false;
 
-  TRACE_ALLOC(("assigning free register %s to %d\n",
-               Location::RegisterLocation(candidate).Name(),
-               unallocated->vreg()));
+  TRACE_ALLOC(OS::Print("assigning free register "));
+  TRACE_ALLOC(Location::RegisterLocation(candidate).Print());
+  TRACE_ALLOC(OS::Print(" to %d\n", unallocated->vreg()));
 
   if (free_until != kMaxPosition) {
     // There was an intersection. Split unallocated.
-    TRACE_ALLOC(("  splitting at %d\n", free_until));
+    TRACE_ALLOC(OS::Print("  splitting at %d\n", free_until));
     LiveRange* tail = unallocated->SplitAt(free_until);
     AddToUnallocated(tail);
   }
 
   cpu_regs_[candidate].Add(unallocated);
   unallocated->set_assigned_location(Location::RegisterLocation(candidate));
 
   return true;
 }
 
@@ skipping 20 matching lines @@
     }
   }
 
   if (free_until < register_use->pos()) {
     // Can't acquire free register. Spill until we really need one.
     ASSERT(unallocated->Start() < ToInstructionStart(register_use->pos()));
     SpillBetween(unallocated, unallocated->Start(), register_use->pos());
     return;
   }
 
-  TRACE_ALLOC(("assigning blocked register %s to live range %d until %d\n",
-               Location::RegisterLocation(candidate).Name(),
-               unallocated->vreg(),
-               blocked_at));
+  TRACE_ALLOC(OS::Print("assigning blocked register "));
+  TRACE_ALLOC(Location::RegisterLocation(candidate).Print());
+  TRACE_ALLOC(OS::Print(" to live range %d until %d\n",
+                        unallocated->vreg(), blocked_at));
 
   if (blocked_at < unallocated->End()) {
     LiveRange* tail = SplitBetween(unallocated,
                                    unallocated->Start(),
                                    blocked_at);
     AddToUnallocated(tail);
   }
 
   AssignNonFreeRegister(unallocated, candidate);
 }
@@ skipping 136 matching lines @@
 }
 
 
 void FlowGraphAllocator::ConvertUseTo(UsePosition* use, Location loc) {
   ASSERT(use->location_slot() != NULL);
   Location* slot = use->location_slot();
   ASSERT(slot->IsUnallocated());
   ASSERT((slot->policy() == Location::kRequiresRegister) ||
          (slot->policy() == Location::kPrefersRegister) ||
          (slot->policy() == Location::kAny));
-  TRACE_ALLOC(("  use at %d converted to %s\n", use->pos(), loc.Name()));
+  TRACE_ALLOC(OS::Print("  use at %d converted to ", use->pos()));
+  TRACE_ALLOC(loc.Print());
+  TRACE_ALLOC(OS::Print("\n"));
   *slot = loc;
 }
 
 
 void FlowGraphAllocator::ConvertAllUses(LiveRange* range) {
   if (range->vreg() == kNoVirtualRegister) return;
-  TRACE_ALLOC(("range [%d, %d) for v%d has been allocated to %s:\n",
-               range->Start(),
-               range->End(),
-               range->vreg(),
-               range->assigned_location().Name()));
+  TRACE_ALLOC(OS::Print("range [%d, %d) for v%d has been allocated to ",
+                        range->Start(), range->End(), range->vreg()));
+  TRACE_ALLOC(range->assigned_location().Print());
+  TRACE_ALLOC(OS::Print(":\n"));
   ASSERT(!range->assigned_location().IsInvalid());
   const Location loc = range->assigned_location();
   for (UsePosition* use = range->first_use(); use != NULL; use = use->next()) {
     ConvertUseTo(use, loc);
   }
 }
 
 
 void FlowGraphAllocator::AdvanceActiveIntervals(const intptr_t start) {
   for (intptr_t reg = 0; reg < kNumberOfCpuRegisters; reg++) {
@@ skipping 60 matching lines @@
     if (cpu_regs_[i].length() == 1) {
       LiveRange* range = cpu_regs_[i][0];
       range->finger()->Initialize(range);
     }
   }
 
   while (!unallocated_.is_empty()) {
     LiveRange* range = unallocated_.Last();
     unallocated_.RemoveLast();
     const intptr_t start = range->Start();
-    TRACE_ALLOC(("Processing live range for vreg %d starting at %d\n",
-                 range->vreg(),
-                 start));
+    TRACE_ALLOC(OS::Print("Processing live range for vreg %d starting at %d\n",
+                          range->vreg(),
+                          start));
 
     // TODO(vegorov): eagerly spill liveranges without register uses.
     AdvanceActiveIntervals(start);
 
     if (!AllocateFreeRegister(range)) {
       AllocateAnyRegister(range);
     }
   }
 
   // All allocation decisions were done.
   ASSERT(unallocated_.is_empty());
 
   // Finish allocation.
   AdvanceActiveIntervals(kMaxPosition);
-  TRACE_ALLOC(("Allocation completed\n"));
+  TRACE_ALLOC(OS::Print("Allocation completed\n"));
 }
 
 
 void FlowGraphAllocator::ConnectSplitSiblings(LiveRange* parent,
                                               BlockEntryInstr* source_block,
                                               BlockEntryInstr* target_block) {
-  TRACE_ALLOC(("Connect source_block=%d, target_block=%d\n",
-               source_block->block_id(),
-               target_block->block_id()));
+  TRACE_ALLOC(OS::Print("Connect source_block=%d, target_block=%d\n",
+                        source_block->block_id(),
+                        target_block->block_id()));
   if (parent->next_sibling() == NULL) {
     // Nothing to connect. The whole range was allocated to the same location.
-    TRACE_ALLOC(("range %d has no siblings\n", parent->vreg()));
+    TRACE_ALLOC(OS::Print("range %d has no siblings\n", parent->vreg()));
     return;
   }
 
   const intptr_t source_pos = source_block->end_pos() - 1;
   ASSERT(IsInstructionEndPosition(source_pos));
 
   const intptr_t target_pos = target_block->start_pos();
 
   Location target;
   Location source;
@@ skipping 16 matching lines @@
       ASSERT(target.IsInvalid());
       target = range->assigned_location();
 #if defined(DEBUG)
       target_cover = range;
 #endif
     }
 
     range = range->next_sibling();
   }
 
-  TRACE_ALLOC(("connecting [%d, %d) [%s] to [%d, %d) [%s]\n",
-               source_cover->Start(), source_cover->End(), source.Name(),
-               target_cover->Start(), target_cover->End(), target.Name()));
+  TRACE_ALLOC(OS::Print("connecting [%d, %d) [",
+                        source_cover->Start(), source_cover->End()));
+  TRACE_ALLOC(source.Print());
+  TRACE_ALLOC(OS::Print("] to [%d, %d) [",
+                        target_cover->Start(), target_cover->End()));
+  TRACE_ALLOC(target.Print());
+  TRACE_ALLOC(OS::Print("]\n"));
 
   // Siblings were allocated to the same register.
   if (source.Equals(target)) return;
 
   // Values are eagerly spilled. Spill slot already contains appropriate value.
   if (target.IsStackSlot()) {
     ASSERT(parent->spill_slot().Equals(target));
     return;
   }
 
   Instruction* last = source_block->last_instruction();
   if ((last->SuccessorCount() == 1) && !source_block->IsGraphEntry()) {
     ASSERT(last->IsGoto());
     last->AsGoto()->GetParallelMove()->AddMove(target, source);
   } else {
     target_block->GetParallelMove()->AddMove(target, source);
   }
 }
 
 
 void FlowGraphAllocator::ResolveControlFlow() {
   // Resolve linear control flow between touching split siblings
   // inside basic blocks.
   for (intptr_t vreg = 0; vreg < live_ranges_.length(); vreg++) {
     LiveRange* range = live_ranges_[vreg];
     if (range == NULL) continue;
 
     while (range->next_sibling() != NULL) {
       LiveRange* sibling = range->next_sibling();
-      TRACE_ALLOC(("connecting [%d, %d) [%s] to [%d, %d) [%s]\n",
-                  range->Start(), range->End(),
-                  range->assigned_location().Name(),
-                  sibling->Start(), sibling->End(),
-                  sibling->assigned_location().Name()));
+      TRACE_ALLOC(OS::Print("connecting [%d, %d) [",
+                            range->Start(), range->End()));
+      TRACE_ALLOC(range->assigned_location().Print());
+      TRACE_ALLOC(OS::Print("] to [%d, %d) [",
+                            sibling->Start(), sibling->End()));
+      TRACE_ALLOC(sibling->assigned_location().Print());
+      TRACE_ALLOC(OS::Print("]\n"));
       if ((range->End() == sibling->Start()) &&
           !sibling->assigned_location().IsStackSlot() &&
           !range->assigned_location().Equals(sibling->assigned_location()) &&
           !IsBlockEntry(range->End())) {
         AddMoveAt(sibling->Start(),
                   sibling->assigned_location(),
                   range->assigned_location());
       }
       range = sibling;
     }
@@ skipping 61 matching lines @@
     OS::Print("-- [after ssa allocator] ir [%s] -------------\n",
               function.ToFullyQualifiedCString());
     FlowGraphPrinter printer(Function::Handle(), block_order_, true);
     printer.PrintBlocks();
     OS::Print("----------------------------------------------\n");
   }
 }
 
 
 }  // namespace dart