[MIPS] Add support for debug stub test

tests/debug_stub/debug_stub_test.py

 # Copyright (c) 2012 The Native Client Authors. All rights reserved.
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 import re
 import struct
 import subprocess
 import sys
 import unittest
 import xml.etree.ElementTree
@@ skipping 71 matching lines @@
     ('es', 'I'),
     ('fs', 'I'),
     ('gs', 'I'),
 ]
 
 
 ARM_REG_DEFS = ([('r%d' % regno, 'I') for regno in xrange(16)]
                 + [('cpsr', 'I')])
 
 
+MIPS_REG_DEFS = [
+     ('zero', 'I'),
+     ('at', 'I'),
+     ('v0', 'I'),
+     ('v1', 'I'),
+     ('a0', 'I'),
+     ('a1', 'I'),
+     ('a2', 'I'),
+     ('a3', 'I'),
+     ('t0', 'I'),
+     ('t1', 'I'),
+     ('t2', 'I'),
+     ('t3', 'I'),
+     ('t4', 'I'),
+     ('t5', 'I'),
+     ('t6', 'I'),
+     ('t7', 'I'),
+     ('s0', 'I'),
+     ('s1', 'I'),
+     ('s2', 'I'),
+     ('s3', 'I'),
+     ('s4', 'I'),
+     ('s5', 'I'),
+     ('s6', 'I'),
+     ('s7', 'I'),
+     ('t8', 'I'),
+     ('t9', 'I'),
+     ('k0', 'I'),
+     ('k1', 'I'),
+     ('global_ptr', 'I'),
+     ('stack_ptr', 'I'),
+     ('frame_ptr', 'I'),
+     ('return_addr', 'I'),
+     ('prog_ctr', 'I'),
+]
+
+
 REG_DEFS = {
     'x86-32': X86_32_REG_DEFS,
     'x86-64': X86_64_REG_DEFS,
     'arm': ARM_REG_DEFS,
+    'mips32': MIPS_REG_DEFS,
     }
 
 
 SP_REG = {
     'x86-32': 'esp',
     'x86-64': 'rsp',
     'arm': 'r13',
+    'mips32': 'stack_ptr',
     }
 
 
 IP_REG = {
     'x86-32': 'eip',
     'x86-64': 'rip',
     'arm': 'r15',
+    'mips32': 'prog_ctr',
     }
 
 
 X86_TRAP_FLAG = 1 << 8
 
 # RESET_X86_FLAGS_VALUE is what ASM_WITH_REGS() resets the x86 flags
 # to.  Copied from tests/common/register_set.h.
 RESET_X86_FLAGS_VALUE = (1 << 2) | (1 << 6)
 KNOWN_X86_FLAGS_MASK = (1<<0) | (1<<2) | (1<<6) | (1<<7) | (1<<11) | (1<<8)
 
@@ skipping 94 matching lines @@
 def ReadMemory(connection, address, size):
   reply = connection.RspRequest('m%x,%x' % (address, size))
   assert not reply.startswith('E'), reply
   return DecodeHex(reply)
 
 
 def ReadUint32(connection, address):
   return struct.unpack('I', ReadMemory(connection, address, 4))[0]
 
 
+def SingleSteppingWorks(ARCH):

[Mark Seaborn, 2013/12/26 23:23:43]

Local variables should be lower case (upper case is for global constants), so
either write "(arch)" here (and change function body) or "()" (and have function
body refer to the global).

[petarj, 2013/12/27 12:59:43]

Done, thanks.

+  # Single-stepping is not yet supported on ARM and MIPS.
+  # TODO(eaeltsin):
+  #   http://code.google.com/p/nativeclient/issues/detail?id=2911
+  return ARCH in ('x86-32', 'x86-64')
+
+
 class DebugStubTest(unittest.TestCase):
 
   def test_initial_breakpoint(self):
     # Any arguments to the nexe would work here because we are only
     # testing that we get a breakpoint at the _start entry point.
     with LaunchDebugStub('test_getting_registers') as connection:
       reply = connection.RspRequest('?')
       AssertReplySignal(reply, NACL_SIGTRAP)
 
   def CheckTargetXml(self, connection):
@@ skipping 47 matching lines @@
       self.assertEquals(registers['r8'], 0x80000009)
       # Skip r9 because it is not supposed to be settable or readable
       # by untrusted code.
       self.assertEquals(registers['r10'], 0xa000000b)
       self.assertEquals(registers['r11'], 0xb000000c)
       self.assertEquals(registers['r12'], 0xc000000d)
       self.assertEquals(registers['r13'], 0x12345678)
       self.assertEquals(registers['r14'], 0xe000000f)
       self.assertEquals(registers['cpsr'] & ARM_USER_CPSR_FLAGS_MASK,
                         (1 << 29) | (1 << 27))
+    elif ARCH == 'mips32':
+      # We skip zero register because it cannot be set.
+      self.assertEquals(registers['at'], 0x11000220)
+      self.assertEquals(registers['v0'], 0x22000330)
+      self.assertEquals(registers['v1'], 0x33000440)
+      self.assertEquals(registers['a0'], 0x44000550)
+      self.assertEquals(registers['a1'], 0x55000660)
+      self.assertEquals(registers['a2'], 0x66000770)
+      self.assertEquals(registers['a3'], 0x77000880)
+      self.assertEquals(registers['t0'], 0x88000990)
+      self.assertEquals(registers['t1'], 0x99000aa0)
+      self.assertEquals(registers['t2'], 0xaa000bb0)
+      self.assertEquals(registers['t3'], 0xbb000cc0)
+      self.assertEquals(registers['t4'], 0xcc000dd0)
+      self.assertEquals(registers['t5'], 0xdd000ee0)
+      self.assertEquals(registers['t6'], 0x0ffffff0)
+      self.assertEquals(registers['t7'], 0x3fffffff)
+      # Skip t8 because it cannot be set by untrusted code.
+      self.assertEquals(registers['s0'], 0x11100222)
+      self.assertEquals(registers['s1'], 0x22200333)
+      self.assertEquals(registers['s2'], 0x33300444)
+      self.assertEquals(registers['s3'], 0x44400555)
+      self.assertEquals(registers['s4'], 0x55500666)
+      self.assertEquals(registers['s5'], 0x66600777)
+      self.assertEquals(registers['s6'], 0x77700888)
+      self.assertEquals(registers['s7'], 0x88800999)
+      self.assertEquals(registers['t9'], 0xaaa00bbb)
+      # Skip k0 and k1 registers, since they can be changed by kernel.
+      self.assertEquals(registers['global_ptr'],  0xddd00eee)
+      self.assertEquals(registers['stack_ptr'],   0x2ee00fff)
+      self.assertEquals(registers['frame_ptr'],   0xfff00000)
+      self.assertEquals(registers['return_addr'], 0x0a0a0a0a)
     else:
       raise AssertionError('Unknown architecture')
 
     expected_fault_addr = GetSymbols()['fault_addr']
     if ARCH == 'x86-64':
       expected_fault_addr += registers['r15']
     self.assertEquals(registers[IP_REG[ARCH]], expected_fault_addr)
 
   # Test that we can write registers.
   def CheckWriteRegisters(self, connection):
     if ARCH == 'x86-32':
       reg_name = 'edx'
     elif ARCH == 'x86-64':
       reg_name = 'rdx'
     elif ARCH == 'arm':
       reg_name = 'r0'
+    elif ARCH == 'mips32':
+      reg_name = 'a0'
     else:
       raise AssertionError('Unknown architecture')
 
     # Read registers.
     regs = DecodeRegs(connection.RspRequest('g'))
 
     # Change a register.
     regs[reg_name] += 1
     new_value = regs[reg_name]
 
     # Write registers.
     self.assertEquals(connection.RspRequest('G' + EncodeRegs(regs)), 'OK')
 
     # Read registers. Check for a new value.
     regs = DecodeRegs(connection.RspRequest('g'))
     self.assertEquals(regs[reg_name], new_value)
 
     # TODO: Resume execution and check that changing the registers really
     # influenced the program's execution. This would require changing
     # debugger_test.c.
 
   def CheckReadOnlyRegisters(self, connection):
     if ARCH == 'x86-32':
       sample_read_only_regs = ['cs', 'ds']
     elif ARCH == 'x86-64':
       sample_read_only_regs = ['r15', 'cs', 'ds']
     elif ARCH == 'arm':
       sample_read_only_regs = []
+    elif ARCH == 'mips32':
+      sample_read_only_regs = ['zero']
     else:
       raise AssertionError('Unknown architecture')
 
     for reg_name in sample_read_only_regs:
       # Read registers.
       regs = DecodeRegs(connection.RspRequest('g'))
 
       # Change a register.
       old_value = regs[reg_name]
       regs[reg_name] += 1
@@ skipping 15 matching lines @@
     mem_addr = 0xffff
     resut = connection.RspRequest('m%x,%x' % (mem_addr, 1))
     self.assertEquals(result, 'E03')
 
   # Run tests on debugger_test.c binary.
   def test_debugger_test(self):
     with LaunchDebugStub('test_getting_registers') as connection:
       # Tell the process to continue, because it starts at the
       # breakpoint set at its start address.
       reply = connection.RspRequest('c')
-      if ARCH == 'arm':
+      if ARCH == 'arm' or ARCH == 'mips32':
         # The process should have stopped on a BKPT instruction.
         AssertReplySignal(reply, NACL_SIGTRAP)
       else:
         # The process should have stopped on a HLT instruction.
         AssertReplySignal(reply, NACL_SIGSEGV)
 
       self.CheckTargetXml(connection)
       self.CheckReadRegisters(connection)
       self.CheckWriteRegisters(connection)
       self.CheckReadOnlyRegisters(connection)
@@ skipping 63 matching lines @@
       reply = connection.RspRequest(step_command)
       AssertReplySignal(reply, NACL_SIGTRAP)
       self.assertEquals(ParseThreadStopReply(reply)['thread_id'], thread_id)
       ip += size
       regs = DecodeRegs(connection.RspRequest('g'))
       self.assertEqual(regs[IP_REG[ARCH]], ip)
       # The trap flag should be reported as unset.
       self.assertEqual(regs['eflags'] & X86_TRAP_FLAG, 0)
 
   def test_single_step(self):
-    if ARCH == 'arm':
-      # Skip this test because single-stepping is not supported on ARM.
-      # TODO(eaeltsin):
-      #   http://code.google.com/p/nativeclient/issues/detail?id=2911
+    if not SingleSteppingWorks(ARCH):
       return
     with LaunchDebugStub('test_single_step') as connection:
       # We expect test_single_step() to stop at a HLT instruction.
       reply = connection.RspRequest('c')
       AssertReplySignal(reply, NACL_SIGSEGV)
       tid = ParseThreadStopReply(reply)['thread_id']
       # Skip past the single-byte HLT instruction.
       regs = DecodeRegs(connection.RspRequest('g'))
       regs[IP_REG[ARCH]] += 1
       AssertEquals(connection.RspRequest('G' + EncodeRegs(regs)), 'OK')
 
       self.CheckSingleStep(connection, 's', tid)
       # Check that we can continue after single-stepping.
       reply = connection.RspRequest('c')
       self.assertEquals(reply, 'W00')
 
   def test_vCont(self):
     # Basically repeat test_single_step, but using vCont commands.
-    if ARCH == 'arm':
-      # Skip this test because single-stepping is not supported on ARM.
-      # TODO(eaeltsin):
-      #   http://code.google.com/p/nativeclient/issues/detail?id=2911
+    if not SingleSteppingWorks(ARCH):
       return
     with LaunchDebugStub('test_single_step') as connection:
       # Test if vCont is supported.
       reply = connection.RspRequest('vCont?')
       self.assertEqual(reply, 'vCont;s;S;c;C')
 
       # Continue using vCont.
       # We expect test_single_step() to stop at a HLT instruction.
       reply = connection.RspRequest('vCont;c')
       AssertReplySignal(reply, NACL_SIGSEGV)
@@ skipping 18 matching lines @@
 
       # Try to single-step wrong thread.
       reply = connection.RspRequest('vCont;s:%x' % (tid + 2))
       self.assertTrue(reply.startswith('E'))
 
       # Try to single-step all threads.
       reply = connection.RspRequest('vCont;s')
       self.assertTrue(reply.startswith('E'))
 
   def test_interrupt(self):
-    if ARCH == 'arm':
-      # Skip this test because single-stepping is not supported on ARM.
-      # TODO(eaeltsin):
-      #   http://code.google.com/p/nativeclient/issues/detail?id=2911
+    if not SingleSteppingWorks(ARCH):
       return
     func_addr = GetSymbols()['test_interrupt']
     with LaunchDebugStub('test_interrupt') as connection:
       # Single stepping inside syscalls doesn't work. So we need to reach
       # a point where interrupt will not catch the program inside syscall.
       reply = connection.RspRequest('Z0,%x,0' % func_addr)
       self.assertEquals(reply, 'OK')
       reply = connection.RspRequest('c')
       AssertReplySignal(reply, NACL_SIGTRAP)
       reply = connection.RspRequest('z0,%x,0' % func_addr)
@@ skipping 108 matching lines @@
     regs = DecodeRegs(connection.RspRequest('g'))
     if ARCH in ('x86-32', 'x86-64'):
       AssertReplySignal(stop_reply, NACL_SIGSEGV)
       # Skip past the single-byte HLT instruction.
       regs[IP_REG[ARCH]] += 1
     elif ARCH == 'arm':
       AssertReplySignal(stop_reply, NACL_SIGTRAP)
       bundle_size = 16
       assert regs['r15'] % bundle_size == 0, regs['r15']
       regs['r15'] += bundle_size
+    elif ARCH == 'mips32':
+      AssertReplySignal(stop_reply, NACL_SIGTRAP)
+      bundle_size = 16
+      assert regs['prog_ctr'] % bundle_size == 0, regs['prog_ctr']
+      regs['prog_ctr'] += bundle_size
     else:
       raise AssertionError('Unknown architecture')
     AssertEquals(connection.RspRequest('G' + EncodeRegs(regs)), 'OK')
 
   def WaitForTestThreadsToStart(self, connection, symbols):
     # Wait until:
     #  * The main thread starts to modify g_main_thread_var.
     #  * The child thread executes a breakpoint.
     old_value = ReadUint32(connection, symbols['g_main_thread_var'])
     while True:
@@ skipping 74 matching lines @@
   global NM_TOOL
   global SEL_LDR_COMMAND
   ARCH = args.pop(0)
   NM_TOOL = args.pop(0)
   SEL_LDR_COMMAND = args
   unittest.main()
 
 
 if __name__ == '__main__':
   Main()