Add some missing x64 instruction variations.

runtime/vm/assembler_x64.cc

Index: runtime/vm/assembler_x64.cc
===================================================================
--- runtime/vm/assembler_x64.cc	(revision 9573)
+++ runtime/vm/assembler_x64.cc	(working copy)
@@ -872,6 +872,14 @@
 }
 
 
+void Assembler::andq(Register dst, const Address& address) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  EmitOperandREX(dst, address, REX_W);
+  EmitUint8(0x23);
+  EmitOperand(dst & 7, address);
+}
+
+
 void Assembler::andq(Register dst, const Immediate& imm) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitRegisterREX(dst, REX_W);
@@ -888,6 +896,14 @@
 }
 
 
+void Assembler::orq(Register dst, const Address& address) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  EmitOperandREX(dst, address, REX_W);
+  EmitUint8(0x0B);
+  EmitOperand(dst & 7, address);
+}
+
+
 void Assembler::orq(Register dst, const Immediate& imm) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitRegisterREX(dst, REX_W);
@@ -904,6 +920,14 @@
 }
 
 
+void Assembler::xorq(Register dst, const Address& address) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  EmitOperandREX(dst, address, REX_W);
+  EmitUint8(0x33);
+  EmitOperand(dst & 7, address);
+}
+
+
 void Assembler::addl(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   Operand operand(src);
@@ -922,6 +946,14 @@
 }
 
 
+void Assembler::addq(Register dst, const Address& address) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  EmitOperandREX(dst, address, REX_W);
+  EmitUint8(0x03);
+  EmitOperand(dst & 7, address);
+}
+
+
 void Assembler::addl(const Address& address, const Immediate& imm) {
   UNIMPLEMENTED();
 }
@@ -1025,6 +1057,15 @@
 }
 
 
+void Assembler::imulq(Register dst, const Address& address) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  EmitOperandREX(dst, address, REX_W);
+  EmitUint8(0x0F);
+  EmitUint8(0xAF);
+  EmitOperand(dst & 7, address);
+}
+
+
 void Assembler::subq(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   Operand operand(src);