Add some missing x64 instruction variations.

runtime/vm/assembler_x64.cc

 // Copyright (c) 2012, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_X64)
 
 #include "vm/assembler.h"
 #include "vm/heap.h"
 #include "vm/memory_region.h"
@@ skipping 854 matching lines @@
 
 void Assembler::andq(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   Operand operand(src);
   EmitOperandREX(dst, operand, REX_W);
   EmitUint8(0x23);
   EmitOperand(dst & 7, operand);
 }
 
 
+void Assembler::andq(Register dst, const Address& address) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  EmitOperandREX(dst, address, REX_W);
+  EmitUint8(0x23);
+  EmitOperand(dst & 7, address);
+}
+
+
 void Assembler::andq(Register dst, const Immediate& imm) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitRegisterREX(dst, REX_W);
   EmitComplex(4, Operand(dst), imm);
 }
 
 
 void Assembler::orq(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   Operand operand(src);
   EmitOperandREX(dst, operand, REX_W);
   EmitUint8(0x0B);
   EmitOperand(dst & 7, operand);
 }
 
 
+void Assembler::orq(Register dst, const Address& address) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  EmitOperandREX(dst, address, REX_W);
+  EmitUint8(0x0B);
+  EmitOperand(dst & 7, address);
+}
+
+
 void Assembler::orq(Register dst, const Immediate& imm) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitRegisterREX(dst, REX_W);
   EmitComplex(1, Operand(dst), imm);
 }
 
 
 void Assembler::xorq(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   Operand operand(src);
   EmitOperandREX(dst, operand, REX_W);
   EmitUint8(0x33);
   EmitOperand(dst & 7, operand);
 }
 
 
+void Assembler::xorq(Register dst, const Address& address) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  EmitOperandREX(dst, address, REX_W);
+  EmitUint8(0x33);
+  EmitOperand(dst & 7, address);
+}
+
+
 void Assembler::addl(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   Operand operand(src);
   EmitOperandREX(dst, operand, REX_NONE);
   EmitUint8(0x03);
   EmitOperand(dst & 7, operand);
 }
 
 
 void Assembler::addq(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   Operand operand(src);
   EmitOperandREX(dst, operand, REX_W);
   EmitUint8(0x03);
   EmitOperand(dst & 7, operand);
 }
 
 
+void Assembler::addq(Register dst, const Address& address) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  EmitOperandREX(dst, address, REX_W);
+  EmitUint8(0x03);
+  EmitOperand(dst & 7, address);
+}
+
+
 void Assembler::addl(const Address& address, const Immediate& imm) {
   UNIMPLEMENTED();
 }
 
 
 void Assembler::addq(Register reg, const Immediate& imm) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitRegisterREX(reg, REX_W);
   EmitComplex(0, Operand(reg), imm);
 }
@@ skipping 83 matching lines @@
 void Assembler::imulq(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   Operand operand(src);
   EmitOperandREX(dst, operand, REX_W);
   EmitUint8(0x0F);
   EmitUint8(0xAF);
   EmitOperand(dst & 7, operand);
 }
 
 
+void Assembler::imulq(Register dst, const Address& address) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  EmitOperandREX(dst, address, REX_W);
+  EmitUint8(0x0F);
+  EmitUint8(0xAF);
+  EmitOperand(dst & 7, address);
+}
+
+
 void Assembler::subq(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   Operand operand(src);
   EmitOperandREX(dst, operand, REX_W);
   EmitUint8(0x2B);
   EmitOperand(dst & 7, operand);
 }
 
 
 void Assembler::subq(Register reg, const Immediate& imm) {
@@ skipping 814 matching lines @@
 
 const char* Assembler::RegisterName(Register reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfCpuRegisters));
   return cpu_reg_names[reg];
 }
 
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_X64