Merged r11507 into trunk branch.

src/mips/stub-cache-mips.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 4519 matching lines @@
     // Install the new backing store in the JSArray.
     __ sw(elements_reg,
           FieldMemOperand(receiver_reg, JSObject::kElementsOffset));
     __ RecordWriteField(receiver_reg, JSObject::kElementsOffset, elements_reg,
                         scratch1, kRAHasNotBeenSaved, kDontSaveFPRegs,
                         EMIT_REMEMBERED_SET, OMIT_SMI_CHECK);
 
     // Increment the length of the array.
     __ li(length_reg, Operand(Smi::FromInt(1)));
     __ sw(length_reg, FieldMemOperand(receiver_reg, JSArray::kLengthOffset));
+    __ lw(elements_reg,
+          FieldMemOperand(receiver_reg, JSObject::kElementsOffset));
     __ jmp(&finish_store);
 
     __ bind(&check_capacity);
     // Make sure that the backing store can hold additional elements.
     __ lw(scratch1,
           FieldMemOperand(elements_reg, FixedDoubleArray::kLengthOffset));
     __ Branch(&slow, hs, length_reg, Operand(scratch1));
 
     // Grow the array and finish the store.
     __ Addu(length_reg, length_reg, Operand(Smi::FromInt(1)));
     __ sw(length_reg, FieldMemOperand(receiver_reg, JSArray::kLengthOffset));
     __ jmp(&finish_store);
 
     __ bind(&slow);
     Handle<Code> ic_slow = masm->isolate()->builtins()->KeyedStoreIC_Slow();
     __ Jump(ic_slow, RelocInfo::CODE_TARGET);
   }
 }
 
 
 #undef __
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_MIPS