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Issue 10253004: MIPS: Removed unused variables. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 8 years, 8 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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2747 void BinaryOpStub::GenerateSmiCode( 2747 void BinaryOpStub::GenerateSmiCode(
2748 MacroAssembler* masm, 2748 MacroAssembler* masm,
2749 Label* use_runtime, 2749 Label* use_runtime,
2750 Label* gc_required, 2750 Label* gc_required,
2751 SmiCodeGenerateHeapNumberResults allow_heapnumber_results) { 2751 SmiCodeGenerateHeapNumberResults allow_heapnumber_results) {
2752 Label not_smis; 2752 Label not_smis;
2753 2753
2754 Register left = a1; 2754 Register left = a1;
2755 Register right = a0; 2755 Register right = a0;
2756 Register scratch1 = t3; 2756 Register scratch1 = t3;
2757 Register scratch2 = t5;
2758 2757
2759 // Perform combined smi check on both operands. 2758 // Perform combined smi check on both operands.
2760 __ Or(scratch1, left, Operand(right)); 2759 __ Or(scratch1, left, Operand(right));
2761 STATIC_ASSERT(kSmiTag == 0); 2760 STATIC_ASSERT(kSmiTag == 0);
2762 __ JumpIfNotSmi(scratch1, &not_smis); 2761 __ JumpIfNotSmi(scratch1, &not_smis);
2763 2762
2764 // If the smi-smi operation results in a smi return is generated. 2763 // If the smi-smi operation results in a smi return is generated.
2765 GenerateSmiSmiOperation(masm); 2764 GenerateSmiSmiOperation(masm);
2766 2765
2767 // If heap number results are possible generate the result in an allocated 2766 // If heap number results are possible generate the result in an allocated
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3452 __ TailCallExternalReference(ExternalReference(RuntimeFunction(), 3451 __ TailCallExternalReference(ExternalReference(RuntimeFunction(),
3453 masm->isolate()), 3452 masm->isolate()),
3454 1, 3453 1,
3455 1); 3454 1);
3456 } else { 3455 } else {
3457 if (!CpuFeatures::IsSupported(FPU)) UNREACHABLE(); 3456 if (!CpuFeatures::IsSupported(FPU)) UNREACHABLE();
3458 CpuFeatures::Scope scope(FPU); 3457 CpuFeatures::Scope scope(FPU);
3459 3458
3460 Label no_update; 3459 Label no_update;
3461 Label skip_cache; 3460 Label skip_cache;
3462 const Register heap_number_map = t2;
3463 3461
3464 // Call C function to calculate the result and update the cache. 3462 // Call C function to calculate the result and update the cache.
3465 // Register a0 holds precalculated cache entry address; preserve 3463 // Register a0 holds precalculated cache entry address; preserve
3466 // it on the stack and pop it into register cache_entry after the 3464 // it on the stack and pop it into register cache_entry after the
3467 // call. 3465 // call.
3468 __ Push(cache_entry, a2, a3); 3466 __ Push(cache_entry, a2, a3);
3469 GenerateCallCFunction(masm, scratch0); 3467 GenerateCallCFunction(masm, scratch0);
3470 __ GetCFunctionDoubleResult(f4); 3468 __ GetCFunctionDoubleResult(f4);
3471 3469
3472 // Try to update the cache. If we cannot allocate a 3470 // Try to update the cache. If we cannot allocate a
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7676 __ Ret(USE_DELAY_SLOT); 7674 __ Ret(USE_DELAY_SLOT);
7677 __ mov(v0, a0); 7675 __ mov(v0, a0);
7678 } 7676 }
7679 7677
7680 7678
7681 #undef __ 7679 #undef __
7682 7680
7683 } } // namespace v8::internal 7681 } } // namespace v8::internal
7684 7682
7685 #endif // V8_TARGET_ARCH_MIPS 7683 #endif // V8_TARGET_ARCH_MIPS
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