MIPS: Do the qNaN fixup at de-serialization time.

src/mips/assembler-mips.cc

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 2119 matching lines @@
     return reinterpret_cast<Address>(
         (GetImmediate16(instr1) << 16) | GetImmediate16(instr2));
   }
 
   // We should never get here, force a bad address if we do.
   UNREACHABLE();
   return (Address)0x0;
 }
 
 
-#define MIPS_QNAN_HI 0x7ff7ffff
-#define MIPS_QNAN_LO 0xffffffff
-
-
+// MIPS and ia32 use opposite encoding for qNaN and sNaN, such that ia32
+// qNaN is a MIPS sNaN, and ia32 sNaN is MIPS qNaN. If running from a heap
+// snapshot generated on ia32, the resulting MIPS sNaN must be quieted.
+// OS::nan_value() returns a qNaN.
 void Assembler::QuietNaN(HeapObject* object) {
-  // Mips has a different encoding of qNaN than ia32, so any heap NaN built
-  // with simulator must be re-encoded for the snapshot. Performance hit not
-  // critical at mksnapshot/build time.  We can't use set_value because that
-  // will put the NaN in an fp register, which changes the bits.
-  uint64_t mips_qnan_bits =
-      (static_cast<uint64_t>(MIPS_QNAN_HI) << 32) | MIPS_QNAN_LO;
-  Address value_ptr = object->address() + HeapNumber::kValueOffset;
-  memcpy(value_ptr, &mips_qnan_bits, sizeof(mips_qnan_bits));
+  HeapNumber::cast(object)->set_value(OS::nan_value());
 }
 
 
 // On Mips, a target address is stored in a lui/ori instruction pair, each
 // of which load 16 bits of the 32-bit address to a register.
 // Patching the address must replace both instr, and flush the i-cache.
 //
 // There is an optimization below, which emits a nop when the address
 // fits in just 16 bits. This is unlikely to help, and should be benchmarked,
 // and possibly removed.
@@ skipping 123 matching lines @@
   }
 
   if (patched) {
       CPU::FlushICache(pc+2, sizeof(Address));
   }
 }
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_MIPS