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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions are | 5 // modification, are permitted provided that the following conditions are |
6 // met: | 6 // met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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2130 return reinterpret_cast<Address>( | 2130 return reinterpret_cast<Address>( |
2131 (GetImmediate16(instr1) << 16) | GetImmediate16(instr2)); | 2131 (GetImmediate16(instr1) << 16) | GetImmediate16(instr2)); |
2132 } | 2132 } |
2133 | 2133 |
2134 // We should never get here, force a bad address if we do. | 2134 // We should never get here, force a bad address if we do. |
2135 UNREACHABLE(); | 2135 UNREACHABLE(); |
2136 return (Address)0x0; | 2136 return (Address)0x0; |
2137 } | 2137 } |
2138 | 2138 |
2139 | 2139 |
2140 #define MIPS_QNAN_HI 0x7ff7ffff | |
2141 #define MIPS_QNAN_LO 0xffffffff | |
2142 | |
2143 | |
2144 void Assembler::QuietNaN(HeapObject* object) { | |
2145 // Mips has a different encoding of qNaN than ia32, so any heap NaN built | |
2146 // with simulator must be re-encoded for the snapshot. Performance hit not | |
2147 // critical at mksnapshot/build time. | |
2148 uint64_t mips_qnan_bits = | |
2149 (static_cast<uint64_t>(MIPS_QNAN_HI) << 32) | MIPS_QNAN_LO; | |
2150 Address value_ptr = object->address() + HeapNumber::kValueOffset; | |
Vyacheslav Egorov (Chromium)
2012/04/12 09:22:05
please comment why accessors do not work.
| |
2151 memcpy(value_ptr, &mips_qnan_bits, sizeof(mips_qnan_bits)); | |
2152 } | |
2153 | |
2154 | |
2140 // On Mips, a target address is stored in a lui/ori instruction pair, each | 2155 // On Mips, a target address is stored in a lui/ori instruction pair, each |
2141 // of which load 16 bits of the 32-bit address to a register. | 2156 // of which load 16 bits of the 32-bit address to a register. |
2142 // Patching the address must replace both instr, and flush the i-cache. | 2157 // Patching the address must replace both instr, and flush the i-cache. |
2143 // | 2158 // |
2144 // There is an optimization below, which emits a nop when the address | 2159 // There is an optimization below, which emits a nop when the address |
2145 // fits in just 16 bits. This is unlikely to help, and should be benchmarked, | 2160 // fits in just 16 bits. This is unlikely to help, and should be benchmarked, |
2146 // and possibly removed. | 2161 // and possibly removed. |
2147 void Assembler::set_target_address_at(Address pc, Address target) { | 2162 void Assembler::set_target_address_at(Address pc, Address target) { |
2148 Instr instr2 = instr_at(pc + kInstrSize); | 2163 Instr instr2 = instr_at(pc + kInstrSize); |
2149 uint32_t rt_code = GetRtField(instr2); | 2164 uint32_t rt_code = GetRtField(instr2); |
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2270 } | 2285 } |
2271 | 2286 |
2272 if (patched) { | 2287 if (patched) { |
2273 CPU::FlushICache(pc+2, sizeof(Address)); | 2288 CPU::FlushICache(pc+2, sizeof(Address)); |
2274 } | 2289 } |
2275 } | 2290 } |
2276 | 2291 |
2277 } } // namespace v8::internal | 2292 } } // namespace v8::internal |
2278 | 2293 |
2279 #endif // V8_TARGET_ARCH_MIPS | 2294 #endif // V8_TARGET_ARCH_MIPS |
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